Common-Clock Flip-Flop Layout for Smaller Chip Area

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Solution Overview

Problem

The challenge is to design an electronic circuit with a flip-flop that occupies a small area, as the arrangement of flip-flops in mobile devices significantly affects the chip size, and existing designs vary in area due to different arrangements, leading to inefficiencies in space utilization and power consumption.

Innovation Solution

The proposed solution involves arranging flip-flops with a common clock generator between master and slave latches, minimizing routing metal and power consumption, and using multiplexers to efficiently manage signals, thereby reducing the overall area and power usage of the electronic circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If flip-flops are arranged in conventional configurations, then the circuit functionality is achieved, but the chip area occupied by flip-flops increases

Engineering Contradiction:

Improvechip areaVSAvoidflip-flop arrangement complexity

Core Design Contradiction:

Area of moving objectVSDevice complexity

Solution Approach 1:

The patent merges the clock generator functionality into a shared resource that serves multiple flip-flops simultaneously. Instead of each flip-flop having its own clock generator, a single clock generator is positioned between master and slave latches to provide clock signals to multiple flip-flops, reducing the total area occupied by clock generation circuits.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The clock generator is designed as a universal component that can serve multiple flip-flops in different configurations. The same clock generator structure can support various flip-flop arrangements (master-slave, edge-triggered, etc.), making the design more area-efficient while maintaining functionality across different operational modes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If more routing metal is used to connect flip-flop components, then signal transmission is improved, but power consumption increases

Engineering Contradiction:

Improvesignal transmissionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent optimizes routing by placing the clock generator locally between master and slave latches, minimizing the distance clock signals must travel. This local positioning reduces the length of routing metal required while ensuring reliable signal transmission to all flip-flops in the configuration.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The clock generator acts as an intermediary component positioned strategically between master and slave latches. This intermediary placement optimizes the routing path, reducing the total metal required for signal distribution while maintaining signal integrity and minimizing power consumption through shorter connection paths.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10673420B2Electronic circuit including flip-flop using common clock

Publication Date: 2020.06.02 SAMSUNG ELECTRONICS CO LTD

AI summary

An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.