Common-Clock RF Transceiver Integration for Lower Chip Area
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Solution Overview
Problem
The integration of growing quantities of receive and transmit paths in wireless communications devices results in large chip areas and high power consumption due to numerous hardware connections between radio frequency and baseband chips, exacerbated by technologies like MIMO and carrier aggregation.
Innovation Solution
A wireless transceiver apparatus integrates a digital interface architecture with a common clock phase-locked loop, incorporating an analog to digital converter, digital to analog converter, and serializer/deserializer within the radio frequency chip, reducing hardware connections and power consumption by using serial digital signals and a shared clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple receive and transmit paths are integrated into wireless communications device, then communication capability is improved, but chip area and power consumption increase
Solution Approach 1:
The patent merges the clock phase-locked loop circuits into the radio frequency chip, integrating functions that were previously separated between radio frequency and baseband chips. This consolidation reduces the total chip area by eliminating redundant components and inter-chip connections, while maintaining support for multiple receive and transmit paths through shared clock resources.
Solution Approach 2:
The patent implements a universal clock phase-locked loop system that serves multiple receive and transmit paths simultaneously. The clock circuitry is designed to provide synchronized timing signals to various communication paths, allowing a single chip to handle multiple functions (carrier aggregation, MIMO) without proportionally increasing area or power consumption.
2Adaptability or versatility
If multiple receive and transmit paths are integrated into wireless communications device, then communication capability is improved, but power consumption increases
Solution Approach 1:
The patent combines clock phase-locked loop functions into the radio frequency chip, reducing power consumption by eliminating redundant clock circuits in separate baseband chips. The integrated design allows shared use of clock resources across multiple communication paths, thereby reducing overall power consumption while maintaining enhanced communication capabilities.
3Device complexity
If analog interface is used between radio frequency chip and baseband chip, then signal processing is simplified, but hardware connections and chip area increase
Solution Approach 1:
The patent merges clock generation and distribution functions into the radio frequency chip, reducing the number of external connections and inter-chip interfaces required. This integration simplifies the overall system architecture by eliminating the need for separate baseband clock circuits, thereby reducing chip area and hardware complexity while maintaining simplified signal processing.
Data Source
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AI summary
Embodiments of this application disclose a wireless transceiver apparatus. The apparatus includes a radio frequency receiver, a radio frequency transmitter, a first serializer/deserializer, and a common clock phase-locked loop. The radio frequency receiver, the radio frequency transmitter, the first serializer/deserializer, and the common clock phase-locked loop are integrated in a radio frequency chip. The radio frequency receiver includes a down converter and an analog to digital converter. The radio frequency transmitter includes an up converter and a digital to analog converter. The first serializer/deserializer is configured to provide a serial digital interface with a baseband chip for the radio frequency chip. Coupled to the analog to digital converter, the digital to analog converter, and the first serializer/deserializer separately, the common clock phase-locked loop is configured to provide a clock signal for the analog to digital converter, the digital to analog converter, and the first serializer/deserializer. The wireless transceiver apparatus can reduce an area and/or power consumption of a chip.