Common Conductive Layer for Chip-to-Chip Signal Transmission
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Solution Overview
Problem
Current 3D IC technologies face challenges such as increased complexity, parameter shifting, and difficulty in integrating different fabrication techniques, leading to low yield rates and high costs, particularly due to the need for extensive wire bonding and flip chip technologies that result in longer transmission distances and noise coupling.
Innovation Solution
A chip-to-chip multi-signaling communication system utilizing a common conductive layer that directly connects chips with conductive material, allowing for high-density signal transmission without the need for extensive interconnections, and eliminating the back-end process by using conductive glue as the common conductive medium.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional point-to-point wire bonding or flip chip technology is used for chip-to-chip connection, then connection between chips is achieved, but transmission distance becomes long and noise coupling increases
Solution Approach 1:
The patent introduces a common conductive layer as an intermediary medium between chips. Instead of direct point-to-point connections, multiple chips connect through this shared conductive layer, which acts as a mediator for signal transmission. This intermediary approach shortens the effective transmission distance and reduces noise coupling by providing a controlled impedance path.
Solution Approach 2:
The common conductive layer serves multiple functions simultaneously: it provides electrical connection between multiple chips, acts as a reference plane for signal integrity, and enables multi-signaling communication. This universal structure eliminates the need for separate connection paths for each chip pair, reducing overall transmission distance and interference.
2Adaptability or versatility
If extensive interconnections are used to connect multiple chips, then chip-to-chip communication is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple individual connection paths into a single common conductive layer. Instead of creating separate interconnection structures for each chip pair, all chips share the same conductive medium, dramatically simplifying the overall device structure while maintaining full communication capability between any chip pairs.
Solution Approach 2:
The patent transitions from planar 2D interconnection to 3D vertical stacking with the common conductive layer positioned between chip layers. This dimensional change allows multiple chips to communicate through a shared intermediate layer, reducing the complexity of lateral routing and enabling more compact, scalable configurations.
3Productivity
If conventional 3D IC technology with wire bonding or flip chip is used, then chip stacking is achieved, but back-end processes are required resulting in low yield rate and high cost
Solution Approach 1:
The patent extracts and eliminates the complex back-end processing steps (wire bonding, flip chip soldering) from the manufacturing flow. By using a common conductive layer that can be integrated during the standard semiconductor fabrication process, the design removes the need for separate, yield-reducing back-end operations.
Solution Approach 2:
The common conductive layer is prepared and integrated into the chip structure during the main fabrication process before final assembly. This preliminary integration of the conductive medium eliminates the need for subsequent complex bonding operations, improving yield and reducing manufacturing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables short-distance signal transmission with high chip-to-chip density, reduced stress, and minimal power consumption, while achieving a high signal-to-noise ratio and eliminating the need for complex back-end processes, thus improving the efficiency and cost-effectiveness of 3D IC integration.
Implementation Method 1
The common conductive layer is a conductive material and is glued directly to the first chip and the second chip; wherein the first pad of the second chip is aligned with the first pad of the first chip for receiving the signal from the first pad of the first chip through the common conductive layer
Data Source
AI summary
A chip-to-chip multi-signaling communication system with common conductive layer, which comprises a first chip, a second chip, and a common conductive layer, is disclosed. The first chip has at least a first metal pad and a second metal pad. The second chip has at least a first metal pad and a second metal pad. The common conductive layer is to a conductive material and glued directly to the first chip and the second chip. Wherein, the first metal pad of the second chip is aligned with the first metal pad of the first chip for receiving the signal from the first metal pad of the first chip through the common conductive layer. The interference generated by other pads of the first and the second chips is suppressed by the design of the pads and the common conductive layer.