Common Control Grid for Semiconductor Wafer Bonding
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Solution Overview
Problem
Current process control methods in semiconductor manufacturing lack effective integration of bonding processes, leading to sub-optimal wafer-to-wafer bonding due to incompatible or poorly optimized grids and shapes, resulting in reduced yield and efficiency.
Innovation Solution
A method involving the determination of a common control grid definition for bonding substrates using metrology data from bonded substrates, which includes co-optimization of scanner and bonding tool corrections, and predictive yield optimization to maximize the number of dies in specification, along with the use of diffraction-based bonding alignment for improved overlay control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate control grids are used for different lithographic apparatus, then each apparatus can operate independently with its own optimization, but the bonding process suffers from incompatible grids leading to reduced yield
Solution Approach 1:
The patent establishes a common control grid definition that serves multiple lithographic apparatus and the bonding process simultaneously. This universal grid enables different scanners to work together in the bonding process with compatible coordinate systems, allowing the grid to function both for individual lithography operations and for integrated wafer-to-wafer bonding operations.
Solution Approach 2:
The patent segments the correction process into two parts: a common control grid definition that provides the baseline coordinate system for all apparatus, and apparatus-specific corrections that address individual scanner characteristics. This segmentation allows maintaining independent optimization for each scanner while ensuring compatibility through the common grid framework.
2Device complexity
If conventional process control methods are used without bonding process integration, then the control process remains simple, but bonding yield and efficiency are reduced due to incompatible grids
Solution Approach 1:
The patent performs preliminary determination of the common control grid definition before the bonding process occurs. This advance preparation ensures that all lithographic apparatus are aligned to compatible coordinate systems beforehand, preventing grid incompatibility issues during bonding and eliminating the need for complex real-time adjustments.
Solution Approach 2:
The patent implements feedback by using metrology data from bonded substrates to refine and optimize the common control grid definition for subsequent bonding operations. This closed-loop approach continuously improves bonding accuracy based on actual measurement results from previous bonding processes.
3Ease of operation
If no co-optimization of scanner and bonding tool corrections is performed, then the process control remains straightforward, but overlay accuracy and yield are compromised
Solution Approach 1:
The patent merges scanner corrections and bonding tool corrections into a unified co-optimization process. By combining these correction mechanisms and coordinating them through the common control grid, the system achieves superior overlay accuracy that neither correction system could achieve independently, while maintaining operational simplicity through integrated control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and efficiency of wafer-to-wafer bonding by optimizing control grids and predictive yield, leading to improved overlay control and increased yield in semiconductor manufacturing.
Implementation Method 1
A fast and non-invasive form of specialized inspection tool is a scatterometer in which a beam of radiation is directed onto a target on the surface of the substrate and properties of the scattered or reflected beam are measured
Implementation Method 2
properties of the scattered or reflected beam are measured
Implementation Method 3
along with the use of diffraction-based bonding alignment for improved overlay control
Data Source
AI summary
A method for controlling a process of manufacturing semiconductor devices, the method including: obtaining a first control grid associated with a first lithographic apparatus used for a first patterning process for patterning a first substrate; obtaining a second control grid associated with a second lithographic apparatus used for a second patterning process for patterning a second substrate; based on the first control grid and second control grid, determining a common control grid definition for a bonding step for bonding the first substrate and second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data including data relating to metrology performed on the bonded substrate; and determining a correction for performance of the bonding step based on the bonded substrate metrology data, the determining a correction including determining a co-optimized correction for the bonding step and for the first patterning process and/or second patterning process.