Common-Drain Back-to-Back FET Current Sensing With Replica FETs

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Power delivery and control in USB and other technologies face challenges in achieving accurate power levels and strict overvoltage and overcurrent protections, particularly in vertical FETs, which are susceptible to electrical damage due to faults and struggle with high-current implementations.

Innovation Solution

A current sensing technique for common-drain dual power FET devices with vertical FETs, using replica FETs sharing a common drain node, allows for accurate current sensing and limiting, implemented in a SiP package with an IC controller, ensuring efficient power delivery and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional current sensing methods are used in vertical FETs, then device complexity is reduced, but measurement precision and reliability deteriorate due to susceptibility to electrical damage and inability to achieve accurate power levels

Engineering Contradiction:
Improvecurrent sensing accuracyVSAvoidFET structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent uses replica FETs that are identical copies of the main power FETs but scaled down in size. These replica FETs replicate the electrical characteristics and current flow of the main FETs, allowing accurate current sensing without directly measuring the high current through the main FETs. The replica FETs are configured in a common-drain arrangement where their sources are connected together, and a sense resistor measures the voltage drop to determine the current flowing through the main FETs.

Inventive Principle:
Principle #26Copying

2Reliability

If back-to-back FET configuration is used, then reliability improves through mutual protection, but device complexity increases due to additional components and configuration

Engineering Contradiction:
Improveprotection against electrical damageVSAvoiddual FET configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the protection function into the existing back-to-back FET configuration by integrating replica FETs within the same structure. The replica FETs share the common-drain node with the main FETs, and the sensing mechanism is embedded within the same circuit path. This combining approach provides overcurrent protection and accurate sensing without requiring completely separate protection circuits, thus improving reliability while limiting the increase in complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If accurate power delivery is implemented with strict overcurrent protection, then reliability improves, but device complexity and difficulty of control increase

Engineering Contradiction:
Improveovercurrent protectionVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback control by continuously monitoring the voltage drop across the sense resistor connected to the common source of the replica FETs. This sensed voltage provides real-time information about the current flowing through the main FETs, which is fed back to the control circuit. The control circuit uses this feedback to dynamically adjust the gate drive signals to the main FETs, ensuring accurate power delivery and preventing overcurrent conditions, thus improving reliability while maintaining manageable control complexity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250337404A1Current sensing implementation for common-drain, back-to-back power switches in vertical FET technology
Publication Date: 2025.10.30 INFINEON TECHNOLOGIES AMERICAS CORP
  • US20250337404A1 patent drawing
  • US20250337404A1 patent drawing
  • US20250337404A1 patent drawing

AI summary

Techniques for load current sensing in common-drain power FET switches are described. In an example embodiment, a power field effect transistor (FET) device includes back-to-back power FETs connected to a common drain node. The power FET device also includes a first replica FET coupled to the common drain node and configured to provide a sense current representative of a load current flowing through the power FET device. The power FET device also includes a second replica FET coupled to the common drain node and configured to provide a sense voltage representative of a voltage of the common drain node. A current sense circuit coupled to the first replica FET and the second replica FET may be configured to use the sense voltage from the second replica FET to draw the sense current through the first replica FET.