Common Drain Pad Insulation for Oxidation-Resistant Chip Packages

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Solution Overview

Problem

Semiconductor packages, particularly chip-scale packages, face challenges in reducing size and improving manufacturing efficiency while maintaining reliable electrical connections and product marking, especially with exposed copper pads that are prone to oxidation and obscured markings.

Innovation Solution

The semiconductor device features a semiconductor die with a common drain pad covered by an electrically insulating layer, allowing for independent switching of transistor devices and providing a stable surface for product marking, using a combination of pad finishing layers and organic insulating materials to prevent oxidation and enhance adhesion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the drain pad is left exposed on the rear side of the semiconductor die, then electrical connection to the drain is enabled, but the copper pad is prone to oxidation and product marking becomes obscured

Engineering Contradiction:

Improveoxidation resistanceVSAvoidelectrical connection accessibility

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The patent applies different surface treatments to different regions of the drain pad. The central portion is covered with an organic layer for oxidation protection and marking, while the peripheral region remains exposed for electrical connection. This local differentiation resolves the contradiction between protection and accessibility.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The organic layer acts as an intermediary substance that provides oxidation protection and marking surface without completely isolating the drain pad. It allows electrical connection through the peripheral exposed region while protecting the central portion, mediating between protection and accessibility requirements.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Volume of moving object

If chip-scale packages are used to reduce size, then package dimensions are minimized, but the exposed copper pads are more susceptible to oxidation and marking becomes difficult

Engineering Contradiction:

Improvepackage sizeVSAvoidpad oxidation resistance

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The organic layer is applied selectively to the central portion of the drain pad in chip-scale packages, providing oxidation protection and marking surface without increasing overall package size. This localized treatment addresses the oxidation and marking issues inherent to miniaturized packages.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20240030502A1Semiconductor device, battery management system and method of producing a semiconductor device

Publication Date: 2024.01.25 INFINEON TECH AUSTRIA AG

AI summary

In an embodiment, a semiconductor device is provided that includes a semiconductor die having a front side, a rear side opposing the front side, and side faces, a first transistor device having a first source pad and a first gate pad on the front side, and a second transistor device having a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.