Common-Drain-Source ESD Protection for High-Voltage Semiconductor Devices

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Solution Overview

Problem

Conventional high-voltage semiconductor devices face challenges in electrostatic discharge (ESD) protection, as existing solutions require significant area, impacting the device's reliability and voltage holding capability.

Innovation Solution

A semiconductor device with an ESD protection structure that incorporates a NMOS transistor, where the drain is shared by the power device's source, and substrate leading-out regions are coupled to the source as ground, forming a common-drain-source structure to minimize area usage and enhance protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a protection structure is added to the source of the high-voltage device to achieve ESD protection, then the ESD protection capability is improved, but the device area increases significantly

Engineering Contradiction:
ImproveESD protection capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the ESD protection function with the existing power device structure by sharing the drain of the NMOS transistor with the source of the power device. This integration allows the ESD protection structure to be formed within the same device footprint, eliminating the need for separate protection structures and thus avoiding significant area increase while maintaining effective ESD protection capability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9953970B2Semiconductor device having ESD protection structure
Publication Date: 2018.04.24 CSMC TECH FAB2 CO LTD
  • US9953970B2 patent drawing
  • US9953970B2 patent drawing
  • US9953970B2 patent drawing

AI summary

The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.