Common Electrode Slits Reduce Parasitic Capacitance in FFS Array Substrates
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Solution Overview
Problem
In fringe field switching (FFS) type TFT-LCDs, the large overlapping region between the common electrode and gate/data lines generates parasitic capacitance, leading to signal delay and decreased display quality, particularly in larger and higher resolution liquid crystal panels, resulting in defects like bright and dark spots.
Innovation Solution
The common electrode is designed with slits in the overlapping regions between the common electrode and the gate/data lines, reducing the overlapping area and thus parasitic capacitance, which decreases signal delay without increasing the driving circuits or altering the substrate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the common electrode is designed with a grid-like shape to widen the view angle, then the view angle range is improved, but parasitic capacitance increases due to large overlapping regions with gate lines and data lines
Solution Approach 1:
The common electrode is divided into multiple isolated island regions separated by slits, rather than forming a continuous grid structure. This segmentation reduces the overlapping area with gate lines and data lines, thereby decreasing parasitic capacitance while still maintaining the ability to generate fringe electric fields for wide view angle performance
Solution Approach 2:
The patent applies different structural characteristics to different regions of the common electrode. The island regions are positioned to overlap with pixel electrodes for effective capacitance coupling, while slits are strategically placed to minimize overlap with gate lines and data lines, creating local quality variations that optimize both view angle and reduce parasitic capacitance
2Manufacturing precision
If the liquid crystal panel size and resolution are increased, then the display quality is improved, but the overlapping region between common electrode and gate/data lines increases, leading to aggravated signal delay
Solution Approach 1:
By segmenting the common electrode into isolated islands with slits between them, the patent reduces the total overlapping area with extensive gate lines and data lines that are inevitable in high-resolution large-size panels. This segmentation approach directly addresses the aggravated signal delay problem by minimizing parasitic capacitance accumulation across the expanded panel area
Solution Approach 2:
The patent extracts or removes the common electrode material in the form of slits from the regions where it would excessively overlap with gate lines and data lines. This extraction reduces the harmful parasitic capacitance without compromising the essential function of the common electrode in generating fringe electric fields for wide view angle display
3Illumination intensity
If transparent materials are used for electrodes to increase light transmittance, then brightness is improved, but parasitic capacitance is generated due to the necessary overlapping structure
Solution Approach 1:
The segmented island structure of the common electrode maintains transparency for high brightness while reducing the overlapping regions with gate lines and data lines. The slits between islands minimize parasitic capacitance formation, allowing the transparent electrode structure to achieve both high light transmittance and low parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the stability of the array substrate, reduces signal delay, and enhances display quality by minimizing parasitic capacitance, making it suitable for larger and higher resolution liquid crystal panels without increasing manufacturing costs.
Implementation Method 1
a large overlapping region is formed between the common electrode of a pixel unit and the underlying gate lines and/or data lines surrounding the pixel unit, and thus parasitic capacitance is generated
Data Source
AI summary
An array substrate is provided. The array substrate comprises a base substrate. A plurality of gate lines, a plurality of data lines, and a common electrode are formed on the base substrate. A plurality of pixel units are defined by the intersecting of the gate lines and the data lines, a pixel electrode is provided in each of the pixel units, the common electrode extends over the pixel units and overlaps the pixel units, and also the common electrode overlaps with the gate lines and the data lines, and an overlapping region slit is provided in the common electrode for each pixel unit in an overlapping region between the common electrode and one of the gate lines and data lines surrounding the pixel unit. Also, a liquid crystal panel and a liquid crystal display comprising an array substrate are also provided.