3D Common-Gate Amplifier Layout for Low-Parasitic AC Grounding
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Solution Overview
Problem
Achieving optimal AC grounding in common-gate amplifier circuits is challenging due to layout parasitics, particularly at high frequencies like millimeter-wave frequencies, which results in reduced maximum frequency and performance losses.
Innovation Solution
The implementation of a 3D transistor structure with vertically stacked metal layers and junction capacitance between wells and substrates, eliminating the need for external capacitors and reducing parasitic inductance by integrating capacitance within the transistor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is placed in near proximity to the gate to ensure AC ground, then AC grounding is improved, but parasitic inductance and resistance increase, reducing maximum frequency
Solution Approach 1:
The patent merges the AC grounding function with the transistor gate structure itself by using the gate metal layer and underlying substrate capacitance, eliminating the need for separate external capacitors. This integration removes interconnection parasitics while maintaining AC grounding functionality.
Solution Approach 2:
The patent transitions from a planar layout with external capacitors to a vertical 3D structure where the gate metal layer is directly connected to the substrate through vias, utilizing the vertical dimension to achieve AC grounding without lateral interconnection parasitics.
2Reliability
If external capacitors are used for AC grounding, then grounding function is achieved, but device area increases due to capacitor wiring and layout
Solution Approach 1:
The AC grounding function is merged into the transistor gate structure itself, using the gate metal layer and substrate capacitance as an integrated AC ground, eliminating the need for separate capacitor components and their associated wiring.
Solution Approach 2:
The transistor gate structure serves its own AC grounding needs through the inherent capacitance between the gate metal layer and the substrate, eliminating the requirement for external grounding components.
3Device complexity
If conventional amplifier circuits are used, then circuit simplicity is maintained, but performance is reduced due to interconnection parasitics at millimeter-wave frequencies
Solution Approach 1:
The patent adopts a vertical 3D transistor structure with stacked metal layers and via connections, transitioning from conventional planar interconnections to vertical pathways that eliminate lateral parasitic inductance and resistance while maintaining circuit functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances stability, increases maximum frequency, and improves large signal performance by effectively AC grounding the gate, reducing parasitic inductance and area requirements, while maintaining high-frequency operation without external capacitor wiring.
Implementation Method 1
At least one capacitance in at least one of a junction between the at least one well and the substrate
Implementation Method 2
a second metal layer overlapped over the first metal layer to form a first capacitor; a third metal layer connected with vias to the first metal layer and overlapped with the second metal layer to form a second capacitor
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a common-gate amplifier circuit and methods of operation. The structure includes at least one well in a substrate, a first metal layer connected to a gate of a transistor circuit, a second metal layer overlapped over the first metal layer to form a capacitor (C3, C4), and a third metal layer connected with vias to the first metal layer and overlapped with the second metal layer to form a second capacitor (C1, C2). At least one capacitance (C5, C6, C7, C8) in at least one of a junction between the at least one well and the substrate and between overlapped metal layers of the first metal layer, the second metal layer, and the third metal layer.