Common Gate BFL Input Circuit for Wider Logic-Level Range

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Solution Overview

Problem

Existing input circuits for III/V MMICs with D-Mode Buffered FET logic face limitations in dynamic range due to the common source switching section, which restricts the voltage noise margin and complicates compatibility with different external digital logic levels, such as 5V CMOS, TTL, LVTTL, 2.5V, and 1.8V, due to the requirement of an additional supply voltage Vss for setting the switch point.

Innovation Solution

The input circuit employs a common gate switching section with a D-mode FET configured as a load and another as a common gate connected between high and low supplies, eliminating the need for Vss and allowing decoupling of the switch point from the dynamic range, thereby maximizing the dynamic range and accommodating various voltage ranges without degrading noise performance. This is achieved through a non-inverting common gate input circuit with a level shift section that includes a source follower and series-connected diodes to set proper voltage levels for D-mode FETs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a common source switching section is used in the input circuit, then the circuit can interface external CMOS digital signals with D-mode III/V BFL, but the dynamic range is limited due to the requirement of an additional supply voltage Vss for setting the switch point

Engineering Contradiction:

Improvecompatibility with external digital logic levelsVSAvoidrequirement of additional supply voltage Vss

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the additional supply voltage Vss from the common source switching section by transitioning to a common gate switching section. This removal of the extra supply requirement simplifies the power architecture while maintaining the ability to interface with various external digital logic levels through the level shift section.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the switching mechanism from common source to common gate configuration, fundamentally altering how the switch point is established. In the common gate configuration, the switch point is naturally determined by the gate voltage reference rather than requiring an additional supply voltage, thereby maximizing dynamic range while maintaining compatibility.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a common source switching section is used, then the input circuit can provide switching function, but the dynamic range is restricted affecting voltage noise margin

Engineering Contradiction:

Improvevoltage noise marginVSAvoidadditional supply voltage Vss

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

By removing the additional supply voltage Vss and transitioning to a common gate configuration, the patent eliminates the constraint that limited dynamic range. The common gate switching section achieves rail-to-rail dynamic range (from Vee to Vdd), thereby improving voltage noise margin without adding circuit complexity.

Inventive Principle:

Principle #2Taking out (Extraction)

3Adaptability or versatility

If the switch point is coupled to the dynamic range in common source configuration, then the circuit operates with available supplies, but increasing dynamic range complicates or limits the design to properly switch for different external digital logic

Engineering Contradiction:

Improveswitching capability for different external digital logicVSAvoiddesign complexity for different voltage supplies

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the input circuit into two independent functional sections: a common gate switching section that maximizes dynamic range using available power supplies, and a level shift section that handles the adaptation to different external digital logic levels. This segmentation allows each section to be optimized independently, simplifying the overall design.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

By changing from common source to common gate configuration, the patent decouples the switch point establishment from the dynamic range limitation. The common gate section operates with maximum dynamic range using only Vdd and Vee, while the level shift section independently adapts to different external logic levels, reducing design complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12028059B2Common gate input circuit for III/V D-mode buffered FET logic (BFL)

Publication Date: 2024.07.02 RAYTHEON CO

AI summary

A common gate input circuit for III/V D-mode Buffered FET Logic (BFL) maximizes the dynamic range to drive a level shift section to set the proper voltage levels to switch the BFL and allows for decoupling of the switch point from the dynamic range. A common gate switching section includes a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common gate connected in series between high and low supplies Vdd and Vee1 (typically ground potential). The gate electrode of FET2 is coupled to Vee1 and the source electrode of FET2 is driven by the external digital signals. This eliminates the additional supply Vss, thus maximizing the dynamic range of the section to switch between Vdd and Vee1 and decouples the dynamic range from the switch point. An input level shift section may shift the Data In to the source electrode of FET2 to shift the switch point and to present a high input impedance.