Common-Gate CFET Work Function Tuning With Dipole-Doped Dielectrics
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the integration of transistors and other components becomes more challenging due to issues with feature size reduction, requiring innovative methods for forming complementary Field-Effect Transistors (CFETs) that address the mismatch in work function levels between p-type and n-type transistors.
Innovation Solution
The formation of CFETs involves sharing a common metal gate with p-type or n-type work function layers, where n-type or p-type dipole dopants are doped into the high-k dielectric layers of respective transistors to adjust their work functions, allowing for the integration of both types of transistors with a single gate electrode, utilizing ex-situ or in-situ doping techniques to achieve desired threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate gate electrodes are used for p-type and n-type transistors to achieve proper work function alignment, then device performance is improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent merges the gate electrodes of p-type and n-type transistors into a single common gate structure. By depositing a first gate electrode over the first gate dielectric and a second gate electrode over the second gate dielectric, then removing portions to expose semiconductor regions, the invention creates an integrated gate system that reduces manufacturing steps while maintaining proper work function alignment through the dipole dopant adjustment
Solution Approach 2:
The patent applies local quality by doping the first gate dielectric with a dipole dopant at a different concentration than the second gate dielectric. This creates localized electrical property differences in specific regions (first and second gate dielectrics) to achieve proper work function alignment for respective p-type and n-type transistors, allowing the use of a common gate electrode material while maintaining device performance
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and control become more difficult
Solution Approach 1:
The patent transitions from planar transistor layouts to vertically stacked three-dimensional structures. By forming first and second gate dielectrics and semiconductor regions in overlapping vertical configurations, the invention achieves higher integration density by utilizing the vertical dimension, allowing multiple transistor pairs to be integrated in a compact footprint while maintaining manufacturable feature sizes
3Reliability
If different work function materials are used for p-type and n-type transistors to achieve proper threshold voltages, then device performance is improved, but process complexity and material deposition steps increase
Solution Approach 1:
The patent changes the electrical parameter of the gate dielectric by doping the first gate dielectric with a dipole dopant at a different concentration than the second gate dielectric. This modifies the effective work function of the gate structure through electrical property adjustment rather than requiring different physical gate materials, simplifying the deposition process while maintaining proper threshold voltage control for p-type and n-type transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient integration of both p-type and n-type transistors with a common gate, reducing manufacturing complexity and improving device performance by aligning work functions, thus enhancing the integration density and performance of semiconductor devices.
Implementation Method 1
n-type or p-type dipole dopants are doped into the high-k dielectric layers of respective transistors to adjust their work functions
Data Source
AI summary
A method includes forming a first semiconductor channel region and a second semiconductor channel region, with the second semiconductor channel region overlapping the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A dipole dopant is incorporated into a first one of the first gate dielectric and the second gate dielectric to a higher atomic percentage, and a second one of the first gate dielectric and the second gate dielectric has a lower atomic percentage of the dipole dopant. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric. The gate electrode and the first gate dielectric form parts of a first transistor, and the gate electrode and the second gate dielectric form parts of a second transistor.