Common Gate Channel Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As integration density in integrated circuit devices increases, parasitic capacitance between conductive elements degrades AC performance, necessitating structures and methods that minimize parasitic capacitance while maintaining high integration density.
Innovation Solution
The integrated circuit device incorporates a unique structure with a first and second channel layer spaced apart in a first direction, each with a surface facing opposite directions, and a gate electrode that exposes only one side surface of the channel layers, reducing the overlapping portion of the source/drain region with the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased, then productivity is improved, but parasitic capacitance increases degrading AC performance
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional wraparound gate structure that extends vertically and laterally around the channel layers. This dimensional change allows the gate to control multiple channel layers simultaneously while reducing the horizontal footprint, thereby increasing integration density without proportionally increasing parasitic capacitance between adjacent gates
Solution Approach 2:
The gate electrode is configured to wrap around and enclose the channel layers, with the gate nested around the channel structure in a wraparound configuration. This nesting arrangement maximizes the gate's control over the channel while minimizing the exposed gate surfaces that would otherwise create parasitic capacitance with surrounding structures
2Object-generated harmful factors
If gate electrode width is reduced to reduce parasitic capacitance, then AC performance is improved, but DC performance may be affected
Solution Approach 1:
The invention compensates for the reduced gate width by extending the gate control into the vertical dimension through the wraparound configuration. The gate wraps around the channel layers, providing electrostatic control from multiple directions (top, bottom, and sides), which maintains effective gate control and DC performance despite the narrower horizontal footprint that reduces parasitic capacitance
3Object-generated harmful factors
If gate electrode exposes channel layer surfaces, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The structure is divided into distinct segments with different functions: the gate electrode is segmented to wrap around the channel layers at specific heights, leaving controlled gaps or exposures at the top and bottom surfaces. This segmentation allows the gate to maintain narrow width for reduced parasitic capacitance while the insulating layer provides manufacturing tolerance buffer zones that reduce alignment precision requirements
Data Source
AI summary
Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first channel layer including a first surface, a second channel layer that is spaced apart from the first channel layer in a first direction and includes a second surface, a first gate electrode and a second gate electrode. The first surface and the second surface may be spaced apart from each other in the first direction and may face opposite directions. The first channel layer may be in the first gate electrode, and the first gate electrode may be absent from the first surface of the first channel layer. The second channel layer may be in the second gate electrode, and the second gate electrode may be absent from the second surface of the second channel layer.