Common-Gate Stack Circuit for Output Impedance and Layout Efficiency
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Solution Overview
Problem
The design of FET cascode and stack-gate circuits faces trade-offs between output headroom and power consumption or layout area, and there is a need for reduced circuit parameter variations in serially connected transistors while maintaining improved output impedance.
Innovation Solution
The stack-gate circuit design connects the semiconductor channels of multiple transistors in series with collectively biased gates, featuring an active zone with distinct threshold-voltage regions and conductive segments to optimize transistor connections and impedance, allowing for reduced variations and improved output impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cascode circuit design is used, then output impedance is improved, but circuit parameter variations increase and layout area increases
Solution Approach 1:
Multiple transistor gates are merged and connected to a common gate voltage node, allowing collective biasing. This merging of gate control mechanisms reduces the number of independent control nodes and simplifies the layout, while maintaining consistent circuit parameters across all transistors in the stack-gate configuration.
Solution Approach 2:
The common gate voltage node serves multiple functions simultaneously: it biases all transistor gates in the stack, provides a single control point for parameter matching, and reduces the overall circuit complexity. This multi-functional approach resolves the contradiction by achieving parameter consistency without proportionally increasing layout area.
2Reliability
If stack-gate configuration with series-connected channels is used, then circuit parameter variations are reduced, but output headroom decreases
Solution Approach 1:
The invention changes the biasing parameter configuration by applying a single gate voltage to all transistors in the stack, rather than using individual gate voltages. This parameter change in the control mechanism achieves reduced parameter variations while the series connection of channels optimizes the voltage distribution to maintain adequate output headroom.
3Reliability
If multiple individual gate voltages are applied to transistors, then output impedance is improved, but circuit complexity and power consumption increase
Solution Approach 1:
Multiple independent gate voltage control lines are merged into a single common gate voltage node. This merging reduces the number of control signals required, simplifies the circuit complexity, and reduces power consumption associated with generating and distributing multiple gate voltages, while the series-connected channel configuration maintains adequate output impedance.
Data Source
AI summary
In an integrated circuit, the gates of a first high-threshold transistor and a first low-threshold transistor are connected together, and the gates of a second high-threshold transistor and a second low-threshold transistor are connected together. The drain of the first high-threshold transistor is conductively connected to the source of the first low-threshold transistor, and the drain of the second high-threshold transistor is conductively connected to the source of the second low-threshold transistor. The gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to the drain of the first low-threshold transistor. The threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. The threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor.