Common Gate Terminal for RRAM Select Devices
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Solution Overview
Problem
Existing memory devices, particularly resistive random access memory (RRAM) cells, face challenges in achieving high current density and selection ratio due to variability in select devices, which affects memory density and control, especially when using three-terminal field effect transistors with separate gate terminals.
Innovation Solution
The implementation of memory cells with a common gate terminal for select devices, which allows for electrical doping of the base semiconductor region and provides electrostatic isolation, reducing variability and increasing memory density by sharing a gate terminal among cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate gate terminals are used for each select device, then individual cell control is improved, but device complexity and area increase
Solution Approach 1:
Multiple select devices share a common gate terminal structure, merging what would otherwise be separate gate terminals into a single shared component. This reduces device complexity and area while maintaining individual cell control through selective voltage application to the common gate.
Solution Approach 2:
The common gate terminal serves multiple select devices simultaneously, making it a universal control element that can selectively control different cells based on the combination of voltages applied to the common gate and the respective source/drain terminals of each select device.
2Productivity
If select devices with high current density capability are used, then memory density is improved, but variability in select device performance increases
Solution Approach 1:
The common gate terminal enables a feedback mechanism where the voltage applied to the common gate can be adjusted based on the desired current density and selection state. This allows for precise control of the select device characteristics, reducing variability by dynamically optimizing the gate voltage to achieve consistent performance across different cells.
Solution Approach 2:
The invention utilizes changes in the voltage parameter applied to the common gate terminal to control and stabilize the performance of select devices. By adjusting the common gate voltage, the effective threshold and current density characteristics of the select devices can be tuned to reduce variability and achieve consistent high-performance operation.
3Productivity
If more select devices are added to increase memory density, then storage capacity is improved, but power dissipation increases
Solution Approach 1:
By merging multiple select devices under a common gate terminal, the power control is consolidated. This allows for simultaneous control of multiple select devices with a single voltage source, reducing the total power dissipation compared to independently controlling each select device with separate gate terminals.
Solution Approach 2:
The common gate terminal enables periodic or selective activation of groups of select devices. By applying voltage to the common gate only when needed for specific memory operations, power dissipation is reduced compared to continuously powered separate gate terminals, while still achieving high memory density through selective access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory density, reduces power dissipation, and improves signal-to-noise ratio during read and write operations by achieving high current density and selection ratios, such as 102:1 or larger, while maintaining low variability in select device control.
Implementation Method 1
The common gate terminal can be used to electrically dope a base semiconductor region located between the first terminal and the second terminal of the select device
Implementation Method 2
provides electrostatic isolation, reducing variability and increasing memory density by sharing a gate terminal among cells
Data Source
AI summary
Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.