Common-Gate Transistor Shared Gate Doped Region Area Reduction
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Solution Overview
Problem
Common-gate transistors occupy a large area in circuit fabrication, which hinders circuit integration.
Innovation Solution
A common-gate transistor design where multiple doped regions are hetero-doped and indirectly connected through a central doped region, allowing two transistors to share a gate doped region and maintain identical electrical properties, reducing the overall area requirement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two independent transistors are used to form a common-gate transistor, then the gate electrical connections are independent and flexible, but the occupied area increases
Solution Approach 1:
The patent merges two transistor gate structures into a single shared gate doped region. The first and second gates are both connected to the same first doped region, eliminating the need for separate gate structures. This merging reduces the total occupied area while maintaining the electrical functionality of the common-gate transistor configuration.
Solution Approach 2:
The first doped region serves multiple functions simultaneously: it acts as the gate for both the first and second transistors, and also functions as a shared electrical connection point. This multi-functionality allows the structure to maintain independent gate control for both transistors while using a single physical gate region, thereby reducing area occupation.
2Area of stationary object
If a shared gate doped region is used, then the occupied area is reduced, but the electrical property consistency must be maintained
Solution Approach 1:
The patent applies local quality by ensuring the shared first doped region has specifically optimized doping characteristics (concentration, depth, lateral dimensions) that are tailored to serve both transistors effectively. By controlling the local electrical properties of the shared gate region, the patent maintains consistent and reliable electrical performance for both transistors despite the shared structure.
Data Source
AI summary
The disclosure discloses a common-gate transistor, a pixel circuit, a driving method and a display, including: a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region; the second doped region, the third doped region, the fourth doped region, and the fifth doped region are indirectly communicated through the first doped region, and the second doped region, the third doped region, and the fourth doped region, the fifth doped region and the first doped region are hetero-doped respectively. The two transistors in the common-gate transistor share one gate doped region, i.e., the first doped region, which can not only save one gate doped region, but also can make the gates of the two transistors have the same electrical parameters, and then the cascode effect of the two transistors is more ideal.