Common Input Driver for Semiconductor Memory Banks
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Solution Overview
Problem
The increasing number of memory banks in semiconductor memory devices leads to a significant increase in the number of input driving blocks, input/output data lines, and control signal lines, causing area burdens and loading issues, particularly with the up global input/output line, which complicates circuit design and increases power consumption.
Innovation Solution
A semiconductor memory device employing a common input driver for multiple memory banks, with shared input driving blocks and control signal lines, reduces the number of input/output data lines and control signal lines, allowing for active operation and minimizing circuit area while maintaining data width options like x8 and x16.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory banks is increased to enhance storage capacity and data transmission, then the storage capacity and interface variety are improved, but the number of input driving blocks, input/output data lines, and control signal lines increases significantly, causing area burden and loading issues
Solution Approach 1:
The patent merges multiple input driving blocks into a single shared input driving block that serves multiple memory banks. This consolidation reduces the total number of input driving blocks and their associated control signal lines, thereby reducing chip area while maintaining the capability to serve multiple memory banks with increased storage capacity
Solution Approach 2:
The shared input driving block is designed to perform multiple functions by serving different memory banks through dynamic configuration. The same input driving block can be selectively connected to different memory banks based on operational requirements, eliminating the need for dedicated input driving blocks for each bank and reducing overall device complexity and area
2Adaptability or versatility
If the number of memory banks is increased to support x8 and x16 data width options, then the interface versatility is improved, but the number of control signal lines and input/output data lines increases, complicating circuit design
Solution Approach 1:
The patent employs dynamic switching mechanisms that allow the same input driving block to be selectively connected to different memory banks based on the required data width mode (x8 or x16). This dynamic reconfiguration capability enables the circuit to adapt to different interface requirements without requiring separate dedicated paths for each mode, thereby maintaining versatility while reducing design complexity
Solution Approach 2:
The system changes operational parameters (connection configurations) rather than physical structure to support different data width options. By dynamically adjusting which memory banks are connected to the shared input driving block, the system can switch between x8 and x16 modes without requiring duplicate circuitry, thus maintaining interface versatility while simplifying the overall circuit design
3Reliability
If dedicated input driving blocks are assigned to each memory bank to ensure reliable data transmission, then the reliability of data transmission is improved, but the number of input driving blocks and control signal lines increases, leading to increased power consumption
Solution Approach 1:
The shared input driving block is designed to handle multiple memory banks sequentially or selectively based on operational needs. Rather than having multiple always-active input driving blocks, the single shared block activates only when needed for specific bank operations, reducing overall power consumption while maintaining reliable data transmission through proper signal timing and control
Data Source
AI summary
A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.