Common Metal Gate Layer for NAND Flash Memory Scalability
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Solution Overview
Problem
The scalability and reliability of semiconductor integrated circuit devices, particularly NAND flash memory devices, are limited by the use of a single thin oxidation process for both high voltage and low voltage transistors, which restricts the growth of LV and tunnel oxides during the same process step.
Innovation Solution
A method is introduced where a common metal gate layer is used for both array and circuitry regions, with a double pre-metal dielectric process applied, allowing for different materials and lithography processes in each region, and a charge trapping layer is disposed on the tunnel oxide to enhance charge storage and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single thin oxidation process is used for both high voltage and low voltage transistors, then process simplicity is maintained, but scalability and reliability are limited
Solution Approach 1:
The patent divides the oxidation process into separate steps: a first oxidation process for growing the tunnel oxide layer, and a second oxidation process for growing the block oxide layer. This segmentation allows each oxide layer to be optimized independently, improving device reliability while maintaining manageable process complexity through systematic division of the manufacturing steps.
2Productivity
If a single thin oxidation process is used for both high voltage and low voltage transistors, then process steps are reduced, but manufacturing precision deteriorates
Solution Approach 1:
The oxidation process is segmented into distinct first and second oxidation steps, each with controlled parameters. The first oxidation process precisely forms the tunnel oxide layer with specific thickness requirements, while the second oxidation process forms the block oxide layer. This segmentation enables precise control over each layer's properties, improving manufacturing precision while maintaining productivity through an organized multi-step approach.
Solution Approach 2:
Different regions of the device receive different oxidation treatments at different times. The tunnel oxide layer receives a first oxidation process with specific parameters optimized for charge trapping, while the block oxide layer receives a second oxidation process with parameters optimized for isolation. This local quality approach ensures each region has the precise properties needed for its function.
3Adaptability or versatility
If separate processing for array and circuitry regions is implemented, then scalability is improved, but device complexity increases
Solution Approach 1:
The patent applies separate processing sequences to array regions and circuitry regions. Array regions undergo processes optimized for flash memory operation, while circuitry regions receive processes optimized for peripheral circuit functionality. This segmentation enables scalable device design where different regions can be independently optimized, and the complexity is managed through systematic regional differentiation rather than monolithic design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the scalability and reliability of NAND flash memory devices by allowing separate processing for array and circuitry regions, avoiding CMP-related issues and enabling efficient charge storage, thereby enhancing the performance and reliability of the semiconductor structure.
Implementation Method 1
an LV oxide and a tunnel oxide may grow on the substrate during the same process step
Implementation Method 2
a charge trapping layer may be disposed on the tunnel oxide
Data Source
AI summary
Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures.