Common N-Well Level Shifter Layout for Latch-Up Control
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Solution Overview
Problem
Integrated circuits with multiple power domains face challenges in signal propagation due to latch-up risks and require significant space for level shifters with PMOS transistors in separately biased n-wells.
Innovation Solution
A level shifting circuit with a bias circuit that biases a common n-well based on the higher of two power supply voltages, avoiding forward biasing of PMOS transistors and reducing the need for separate n-well spacing, thereby minimizing latch-up risks and space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate n-wells are used for PMOS transistors in different power domains, then latch-up risks are reduced, but space requirements increase due to n-well spacing requirements
Solution Approach 1:
The patent combines multiple n-wells into a single common n-well structure that accommodates PMOS transistors from different power domains. This merging eliminates the need for separate n-wells and their associated spacing requirements, thereby reducing the overall area while maintaining latch-up protection through alternative design features.
Solution Approach 2:
The patent introduces an isolation structure as an intermediary element between PMOS transistors operating at different voltage levels within the common n-well. This isolation structure acts as a mediator that prevents latch-up conditions while allowing the compact common n-well configuration, thus resolving the contradiction between area reduction and reliability maintenance.
2Reliability
If multiple PMOS transistors are positioned in separate n-wells, then latch-up protection is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple separate n-well configurations into a single common n-well structure, simplifying the device architecture. This consolidation reduces the complexity of n-well formation, doping processes, and layout design while maintaining reliability through the introduction of isolation structures and careful voltage management.
3Reliability
If n-well spacing is maintained for separate n-wells, then latch-up risks are minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent eliminates the need for precise n-well spacing by merging separate n-wells into a common n-well structure. This approach removes the manufacturing precision challenge associated with maintaining specific spacing between multiple n-wells, as the isolation structures and single n-well configuration provide sufficient protection against latch-up without requiring tight spacing tolerances.
Data Source
AI summary
A method of generating an integrated circuit (IC) layout diagram includes defining first through fourth PMOS transistors in an n-well region, arranging a plurality of conductive regions whereby a bias circuit is configured to include the first and second PMOS transistors and a level shifter is configured to include the third and fourth PMOS transistors, and arranging a plurality of conductive elements whereby a first power domain includes electrical connections to each of the first and third PMOS transistors and a second power domain includes electrical connections to each of the second and fourth PMOS transistors.