Common Parser-Deparser for Modular Packet Processing
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Solution Overview
Problem
Conventional network dataplane programs face inefficiencies due to repeated parsing and reassembly of headers, which consume significant hardware resources and processing time, especially when composed of multiple modules, and many hardware targets lack the architecture to handle repeated parsing and reassembly effectively.
Innovation Solution
A method is introduced to manipulate the intermediate representation of modular packet-processing programs by synthesizing a common parser-deparser, utilizing a directed-acyclic-graph (DAG) to eliminate repeated parsing and deparsing, and efficiently utilize specialized blocks on chip, allowing for simultaneous execution of parsers and deparsers across modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple modules process common headers independently, then each module can perform its specific processing function, but hardware resources and processing time are consumed repeatedly
Solution Approach 1:
The patent merges multiple independent parsers that process common headers into a single shared parser. The parser graph is analyzed to identify common subgraphs representing repeated header parsing operations, and these are consolidated into one parser instance that serves multiple modules, eliminating redundant processing while preserving individual module functionality.
Solution Approach 2:
The shared parser is designed to serve multiple modules simultaneously through a universal interface. The parser graph transformation creates a common parser that can be invoked by multiple modules, allowing one parser to perform the function of what would otherwise require multiple separate parsers, thus improving resource utilization and processing throughput.
2Ease of operation
If parsers and deparsers are executed separately for each module, then modular processing is maintained, but hardware resource consumption increases significantly
Solution Approach 1:
The patent combines multiple module-specific parsers and deparsers into shared resources. By analyzing the parser graph and identifying common processing paths, the system creates shared parser and deparser instances that are reused across modules, reducing the total number of parser/deparser executions while maintaining modular program structure and ease of composition.
Solution Approach 2:
The system performs preliminary analysis of the parser graph to identify and consolidate common parsing operations before execution. This pre-processing step transforms the modular program representation into an optimized form where shared parsers and deparsers are established, allowing subsequent packet processing to benefit from reduced hardware resource consumption without affecting modular programming simplicity.
3Adaptability or versatility
If repeated parsing and reassembly is performed, then each module can process packets independently, but processing time increases due to overhead
Solution Approach 1:
The patent merges repeated parsing operations into a single execution path by consolidating the parser graph. Common headers that would otherwise be parsed multiple times by different modules are parsed once by a shared parser, and the results are made available to all modules that need them, thereby reducing processing time while maintaining independent module execution capability.
Solution Approach 2:
Instead of repeatedly executing the full parsing process for common headers, the system creates copies of the parsed header data and distributes them to modules that require them. This allows modules to access header information without triggering repeated parsing operations, reducing processing time while preserving modular independence.
Data Source
AI summary
A method for manipulating an intermediate representation of a modular packet-processing program is provided. The method includes receiving a plurality of modules configured to be conditionally executed, the plurality of modules including at least two parsers, ordering, topologically, at least two extracted header instances in a state of each of the at least two parsers, mapping the at least two header instances to use a common memory block, constructing a common parser directed-acyclic-graph (DAG), synthesizing a bitwise operation on a header instance validity bit and a packet validity bit of a common state in the common parser DAG, and outputting the common parser DAG into the intermediate representation.