Glitch Suppression Buffers for Common-Path Fault Detection
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Solution Overview
Problem
Dual-core lockstep computer systems face reliability issues due to undetectable faults on common paths of clock, reset, and test signals, which can cause glitches and system crashes in safety-critical automotive applications.
Innovation Solution
The implementation of glitch suppression buffers at the ends of common signal paths for clock, reset, and test signals to suppress glitches before they reach the main and shadow core processors, allowing for reliable operation and fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing buffers are placed on clock, reset, test signals and data signals in dual-core lockstep system, then signal timing is synchronized, but glitches occur on common paths making faults undetectable
Solution Approach 1:
The patent segments the signal path by placing glitch suppression buffers at specific locations on common paths (clock, reset, test signals) before they diverge to main and shadow cores. This segmentation isolates the glitch-prone common path sections from the critical comparison paths, allowing timing buffers to remain on individual core paths for synchronization while preventing glitches from propagating to both cores simultaneously.
Solution Approach 2:
The glitch suppression buffer acts as an intermediary element inserted into common signal paths. It mediates between the signal source and the divergence point to main and shadow cores, filtering out glitches while allowing valid signals to pass through. This intermediary prevents harmful glitches from reaching both cores simultaneously without disrupting the overall timing synchronization achieved by buffers on individual core paths.
2Reliability
If glitch suppression buffers are added to suppress glitches on common paths, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by placing glitch suppression buffers only at specific critical locations on common paths where glitches would affect both cores, rather than uniformly across all signal paths. Timing buffers remain on individual core paths for synchronization. This selective placement provides targeted glitch suppression exactly where needed (at divergence points of common paths) without adding unnecessary complexity to the entire system.
Data Source
AI summary
An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.