Common PHY Architecture for Multi-Protocol Error Correction

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Solution Overview

Problem

As data rates for serial links exceed 32.0 GT/s, existing interconnect architectures face challenges in efficiently managing error correction and latency variations across different protocols like PCIe, CXL, and UPI, leading to inefficiencies in energy consumption and performance.

Innovation Solution

A common physical layer (PHY) is introduced that supports multiple interconnect protocols, dynamically adjusting Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC) mechanisms based on operating conditions to optimize error correction and latency according to specific protocol needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple separate PHYs are used for different interconnect protocols (PCIe, CXL, UPI), then each protocol can have optimized error correction and latency characteristics, but device complexity and energy consumption increase due to redundant error correction mechanisms

Engineering Contradiction:

Improveprotocol-specific error correction optimizationVSAvoidmultiple PHY instances

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a universal PHY architecture that can operate with multiple interconnect protocols (PCIe, CXL, UPI) simultaneously. The common PHY includes configurable error correction mechanisms that can be dynamically adjusted based on the active protocol, eliminating the need for separate dedicated PHY instances for each protocol while maintaining protocol-specific optimization

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges previously separate PHY instances for different protocols into a single common PHY. The error correction functionality is consolidated into shared hardware resources that can be dynamically allocated and configured based on protocol requirements, reducing overall device complexity while preserving protocol-specific performance characteristics

Inventive Principle:

Principle #5Merging (Combining)

2Loss of time

If protocol-specific PHYs are used, then latency can be optimized for each protocol, but energy consumption increases due to redundant error correction mechanisms operating simultaneously

Engineering Contradiction:

Improveprotocol-specific latencyVSAvoidenergy consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic configuration of error correction mechanisms within the common PHY. The error correction strength, latency parameters, and operational modes can be dynamically adjusted based on which protocol is currently active, allowing the system to optimize for low latency when needed while reducing error correction overhead to save energy when protocol-specific optimizations are less critical

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes operational parameters of the error correction mechanisms based on the active protocol. Different protocols can have different error correction codes, block sizes, and retransmission parameters applied, allowing each protocol to operate with optimal latency characteristics while sharing the same physical layer hardware

Inventive Principle:

Principle #35Parameter changes

3Reliability

If redundant error correction mechanisms are implemented for each protocol, then reliability is improved, but device complexity and energy consumption increase

Engineering Contradiction:

Improveerror correction capabilityVSAvoidenergy waste

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The common PHY includes intelligent protocol detection and automatic configuration capabilities. When a specific protocol is detected, the system automatically configures the appropriate error correction parameters and activates only the necessary correction mechanisms for that protocol, eliminating the need for all error correction mechanisms to operate simultaneously and reducing energy waste

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS20250307068A1Multi-protocol support on common physical layer

Publication Date: 2025.10.02 INTEL CORP

AI summary

Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC/ECC combinations can be used based on the interconnect protocol and the link operational conditions.