Common Power Information Format for IC Design
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Solution Overview
Problem
Conventional IC design flows struggle to effectively implement and verify advanced power management techniques, such as multiple power domains with power shut-off, across various stages of the design process, leading to gaps in RTL to GDSII implementation and verification, and limitations in using these techniques for functional verification and low power designs.
Innovation Solution
A single file format, Common Power Information Format (CPIF), captures power-related design intent, constraints, and technology information, enabling EDA tools to access and utilize this information throughout the design flow, from RTL to physical implementation, for designing and verifying integrated circuits with specialized power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional IC design flows are used, then design implementation proceeds through standard stages, but power management techniques cannot be effectively implemented or verified across various stages
Solution Approach 1:
The patent creates a universal power domain annotation system that can be applied across multiple design stages (RTL, synthesis, physical implementation) using a common file format. This allows the same power management techniques to be implemented and verified throughout the entire design flow, rather than being limited to specific stages.
Solution Approach 2:
The patent introduces an intermediary power domain annotation file format that bridges the gap between different design tools and stages. This intermediary format allows power management information to be exchanged and processed by various EDA tools throughout the design flow, enabling consistent power domain implementation across stages.
2Reliability
If advanced power management techniques are implemented at physical level only, then power control can be achieved, but RTL verification and functional verification are limited
Solution Approach 1:
The patent enables power domain annotations to be applied at the RTL stage before physical implementation. This preliminary action allows verification of power management logic and detection of potential issues early in the design process, rather than waiting until the physical implementation stage.
Solution Approach 2:
The patent implements a feedback mechanism where power domain annotations and verification results from physical implementation can be used to refine and verify the RTL design. This bidirectional verification process allows issues to be detected and corrected at both RTL and physical levels, improving overall reliability.
3Loss of energy
If power management techniques are implemented at physical implementation phase only, then leakage power dissipation can be minimized, but design flaws cannot be identified early
Solution Approach 1:
The patent enables power domain annotations to be applied and verified at the RTL stage, allowing design flaws related to power management to be identified and corrected early in the design process. This preliminary verification prevents costly redesigns later in the implementation phase.
Solution Approach 2:
The patent replaces the traditional mechanical approach of implementing power management only at the physical fabrication stage with an information-based approach using annotated design files. This allows virtual verification and optimization of power domains before physical implementation, reducing the need for iterative physical redesigns.
4Adaptability or versatility
If multiple power domains are demarcated with multiple power modes, then power management flexibility is improved, but device complexity increases
Solution Approach 1:
The patent divides the circuit design into multiple independent power domains, each with its own power mode annotations. This segmentation allows each domain to be controlled independently with simple binary power mode indicators, managing complexity through modular organization rather than monolithic control.
Solution Approach 2:
The patent uses parameter changes in the annotation file format to define multiple power modes for different operational scenarios. By encoding power mode information as configurable parameters in the design files, the system achieves flexibility without hardwiring complex control logic into the circuit design.
Data Source
AI summary
A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.