Common-Resonator Dual-Mode Clock for Smooth MHz-kHz Switching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing systems face challenges in reducing area and cost while generating both high performance and low power clock signals, with synchronization difficulties between different clock domains due to the use of separate crystal resonators for MHz and kHz frequencies, leading to increased board space and material costs.

Innovation Solution

A system utilizing a single resonator to generate both frequencies, with a shift register based state machine controlling the switchover between high performance and low power oscillators, allowing the high performance clock to be shut down in low power modes and ensuring the low power clock is always available, using a programmable divider for frequency adjustment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two separate crystal resonators are used for MHz and kHz clocks, then frequency stability is improved, but device area and cost increase

Engineering Contradiction:
Improvefrequency stabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges two separate crystal resonators into a single shared resonator that serves both the MHz high-performance clock and the kHz low-power clock. This consolidation reduces device area and component cost while maintaining frequency stability through careful circuit design that allows the single resonator to be driven by different oscillator circuits depending on the operating mode.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single crystal resonator is designed to perform multiple functions: it can be driven by a high-performance oscillator circuit for MHz operations requiring frequency stability, and simultaneously or alternatively driven by a low-power oscillator circuit for kHz time-keeping operations. The resonator itself becomes a universal component that adapts to different operational requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If two separate crystal resonators are used for MHz and kHz clocks, then frequency stability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvefrequency stabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

By combining the resonator resources, the patent reduces the bill of materials (BOM) cost associated with purchasing and assembling two separate crystal resonators. The single resonator approach simplifies the manufacturing process and reduces component inventory requirements while maintaining the frequency stability needed for both clock domains through shared resonant element design.

Inventive Principle:
Principle #5Merging (Combining)

3Use of energy by moving object

If MHz crystal oscillator is shut down for low power mode, then power consumption is reduced, but startup time increases

Engineering Contradiction:
Improvepower consumptionVSAvoidstartup time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The low-power kHz oscillator continues to run continuously in the background even when the system is in low-power mode, maintaining time-keeping functionality without requiring the MHz oscillator to start up. This preliminary action of keeping the low-power oscillator active eliminates the startup time penalty when transitioning from low-power to high-performance mode, as the system can quickly switch to the MHz oscillator without waiting for it to initialize.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the operational parameters by using two different oscillator circuits with different power consumption characteristics. The low-power oscillator operates continuously at kHz frequencies with minimal power draw, while the high-performance MHz oscillator is activated only when needed. This parameter change allows the system to achieve both low power consumption in sleep mode and fast startup when transitioning to active mode.

Inventive Principle:
Principle #35Parameter changes

4Use of energy by moving object

If low power kHz oscillator is used, then power consumption is reduced, but startup time increases

Engineering Contradiction:
Improvepower consumptionVSAvoidstartup time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The low-power kHz oscillator is kept continuously running in the background as a preliminary action, maintaining system time and readiness without requiring full MHz oscillator startup. This continuous operation eliminates the startup time issue for the low-power oscillator, as it never needs to start up from a stopped state - it simply transitions between active and standby modes while maintaining its oscillation capability.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces device area and cost, enhances flexibility in clock design, and minimizes power consumption in low power states by using a common resonator for both clock signals, ensuring accurate timekeeping and rapid system wake-up without extensive synchronization efforts.

Implementation Method 1

a resonator, a first clock circuit having a first oscillator circuit coupled to the resonator, the first clock circuit for generating a first clock signal having a first frequency in response to the resonator

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS9581973B1Dual mode clock using a common resonator and associated method of use
Publication Date: 2017.02.28 RENESAS ELECTRONICS AMERICA INC
  • US9581973B1 patent drawing
  • US9581973B1 patent drawing
  • US9581973B1 patent drawing

AI summary

An integrated circuit comprising, a resonator, a first clock circuit for generating a first clock signal having a first frequency in response to the resonator, a second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit of the integrated circuit, using a shift register based state machine and utilizing the inertia of the resonator to smoothly transition between the two oscillators, to provide a dual mode clock output signal.