Common Select Line for Semiconductor Memory Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing memory cell operation characteristics and reliability while meeting the demands of reduced size, lower power consumption, and higher performance in modern electronic devices.
Innovation Solution
A semiconductor device structure is proposed, featuring a stack with word lines, bit lines, global bit lines, global word lines, and common select lines, along with select transistors and contact plugs, which allows for controlled coupling between these elements, enabling efficient memory cell operation and random access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate select lines are used for bit line and word line selection, then independent control is achieved, but device complexity and area increase
Solution Approach 1:
The patent combines two separate select lines (first select line for bit line selection and second select line for word line selection) into a single common select line. This common select line controls both the first select transistor (coupling global bit line to bit line) and the second select transistor (coupling global word line to word line) simultaneously, thereby reducing device complexity and area while maintaining functional control capability.
2Measurement precision
If more select transistors are added for independent selection, then selection precision is improved, but device area and complexity increase
Solution Approach 1:
The patent merges the control functions of two select transistors into a single common select line structure. The first select transistor and second select transistor share the same common select line, reducing the total number of select line connections and associated transistors, thereby decreasing device area while preserving random access capability through coordinated control of the shared select line.
3Area of stationary object
If common select line is used for both bit line and word line selection, then device area is reduced, but control flexibility may be limited
Solution Approach 1:
The patent segments the control function by introducing separate control signals for the first select transistor and second select transistor, while sharing the common select line. This allows independent control of bit line selection and word line selection through different control signal combinations, maintaining control flexibility despite the shared physical select line structure.
Solution Approach 2:
The patent implements dynamic control where the common select line can be activated in different operational modes. By dynamically switching the state of the common select line in coordination with respective control signals, the system achieves both area reduction and maintained control flexibility for various memory access patterns.
Data Source
AI summary
Provided herein may be a semiconductor device. The semiconductor device may include a stack including word lines, a bit line penetrating the stack, a global bit line disposed above the stack, global word lines disposed above the stack, a common select line disposed above the stack, a first contact plug coupling the global bit line and the bit line to each other and penetrating the common select line, and second contact plugs coupling the global word lines and the word lines to each other respectively and penetrating the common select line.