Common Source LDMOS Transistor Pair for Low On-Resistance
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Solution Overview
Problem
Existing MOS device technologies cannot integrate monolithically controlled p-channel MOSFET pairs in a common source configuration while achieving the required low on-resistance (Rds,on) and minimizing area, which is essential for battery-operated systems requiring minimal voltage drop and compact size.
Innovation Solution
A semiconductor device with a pair of p-channel laterally diffused metal oxide semiconductor (LDMOS) transistors, where the first and second transistors share a common source electrode, and are integrated using wafer level packaging with conductive bumps or molded into a standard plastic package, allowing for efficient current flow and low resistance switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vertically current flowing MOSFETs with common drain electrodes are used, then specific resistance is improved, but common source configuration cannot be achieved
Solution Approach 1:
The patent inverts the conventional MOSFET structure by switching from vertical current flow with common drain electrodes to lateral current flow with common source electrodes. This inversion allows the device to achieve common source configuration while maintaining low on-resistance through optimized lateral current paths and source electrode design.
2Ease of operation
If individually packaged transistors are used, then transistor control is achieved, but area occupancy increases
Solution Approach 1:
The patent merges two independently controlled MOSFETs into a single integrated device package with shared source electrode and substrate. This combining reduces the total footprint area while maintaining independent gate control through separate gate electrodes, achieving compact size without sacrificing operational independence.
Solution Approach 2:
The integrated device structure serves multiple functions: it provides independent control of two MOSFETs through separate gates, achieves low on-resistance through optimized source connections, and minimizes area occupancy through shared substrate and source electrode. This multi-functional design simultaneously addresses control, performance, and size requirements.
3Loss of energy
If low on-resistance switching is required for high current levels, then voltage drop is reduced, but device area increases
Solution Approach 1:
The patent applies local quality optimization by designing specific regions with different properties: the source electrode and substrate are engineered for low resistance to handle high current, while the overall device footprint is minimized through efficient layout. This localized optimization of conductive paths reduces voltage drop without proportionally increasing total device area.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.