Common Source Line Layer Layout for 3D Memory Wiring Simplification
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Solution Overview
Problem
The complexity of forming memory cells and wire structures in vertically stacked memory devices increases with the number of stacked memory cells, making it difficult to create efficient connections between them.
Innovation Solution
A semiconductor device with a common source line layer that simplifies the wiring structure by integrating the common source line layer, input and output pads, and isolated pads at the same vertical level, using metal materials like tungsten, titanium, or aluminum, and a manufacturing method that forms these components simultaneously to reduce the complexity of the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked memory cells are increased in number, then memory capacity is improved, but the complexity of forming memory cells and wire structures increases
Solution Approach 1:
The patent merges the common source line layer with the input/output pad layer into the same vertical level, creating a unified metal layer that serves both as a source line for memory cells and as an input/output interface. This consolidation reduces the total number of separate wire structures needed, directly addressing the complexity issue while maintaining the ability to support increased memory capacity through vertical stacking.
Solution Approach 2:
The metal layer at the vertical level is designed to perform multiple functions simultaneously: it acts as a common source line for connecting to channel structures in the cell region, serves as an input/output pad for external connections, and provides electrical connectivity across different functional regions. This multi-functionality reduces the need for separate dedicated structures for each function, thereby simplifying the overall wiring structure.
2Quantity of substance
If vertically stacked memory cells are increased in number, then memory capacity is improved, but the difficulty of forming wire structures increases
Solution Approach 1:
The manufacturing process merges the formation of the common source line layer and input/output pad into a single metal deposition and patterning step. By treating these as one unified structure rather than separate layers, the patent reduces the number of manufacturing steps required, making the process easier to execute while supporting higher memory capacities through vertical integration.
Solution Approach 2:
The patent transitions from a planar wiring architecture to a vertical stacking architecture, where the common source line layer and input/output pad coexist at the same vertical level rather than being stacked in multiple horizontal layers. This dimensional reorganization simplifies the manufacturing process by reducing the number of sequential deposition and patterning steps needed, while still accommodating increased memory capacity through vertical cell stacking.
3Device complexity
If common source line layer is integrated with input/output pad at the same vertical level, then wiring structure is simplified, but manufacturing precision requirements increase
Solution Approach 1:
The metal layer is segmented into functionally distinct regions: a common source line portion in the cell region that connects to channel structures, and an input/output pad portion in the input/output region that provides external interfaces. This segmentation allows each region to be optimized for its specific function while being formed in the same metal layer, reducing the overall wiring complexity while managing manufacturing precision requirements through region-specific design considerations.
Data Source
AI summary
A semiconductor device includes a cell region in which a channel structure is disposed and memory cells arranged in three dimensions are disposed, a cell contact region in which a cell contact plug is disposed, a common source line contact region in which a common source line contact plug is disposed, an input and output contact region in which an input and output contact plug is disposed, a word line cut region separating word lines of the cell region from word lines of a neighboring cell region, a common source line layer connecting the channel structure and the common source line contact plug, and an input and output pad connected to the input and output contact plug. The common source line layer and the input and output pad are disposed at the same vertical level.