Memory Cells with Common Source Lines for Compact Footprint
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Solution Overview
Problem
Conventional memory cell arrays require large layouts due to dedicated source lines and high voltage programming, making them unsuitable for small-area applications and limiting their endurance and power efficiency.
Innovation Solution
Implementing memory cells with common source lines and using the Fowler-Nordheim programming technique, which allows for lower voltage operation, reduced current usage, and a smaller footprint, enabling low-power, high-endurance memory devices suitable for small-area applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dedicated source lines are used in conventional memory cell arrays, then programming and data access can be performed, but the layout area increases significantly
Solution Approach 1:
The patent merges the source line function with the bit line structure by configuring bit lines to serve dual purposes: data access during read operations and programming during write operations. This is achieved by applying appropriate voltages to control gates and selecting specific memory cells, allowing the bit line to function as both a data line and a programming line, thereby eliminating the need for separate dedicated source lines and reducing layout area.
Solution Approach 2:
The bit line is designed to perform multiple functions: it serves as a data access line during read operations and as a programming line during write operations. By making the bit line universal, the patent eliminates the need for dedicated source lines, significantly reducing the memory cell array layout area while maintaining full programming and read capabilities.
2Ease of operation
If high voltage programming is used in conventional memory cells, then data can be programmed, but power consumption increases and endurance decreases
Solution Approach 1:
The patent changes the voltage parameters used for programming from high voltage to low voltage operations. By carefully controlling the voltages applied to control gates and bit lines, the patent achieves effective programming at lower voltage levels, reducing power consumption and minimizing stress on memory cells to improve endurance while maintaining programming capability.
Solution Approach 2:
The patent applies partial voltage to the bit line during programming operations, using only the necessary voltage level required to program selected memory cells rather than applying high voltage to all cells. This selective partial action reduces overall power consumption while achieving the programming objective for specific memory locations.
3Ease of operation
If high voltage programming is used in conventional memory cells, then data can be programmed, but program/erase cycling endurance is limited
Solution Approach 1:
The patent changes the voltage parameters from high voltage to low voltage programming, significantly reducing the electrical stress on memory cell structures during programming and erase operations. This parameter change decreases degradation of memory cell components, thereby extending the number of program/erase cycles the memory can endure while maintaining full programming functionality.
4Ease of operation
If conventional memory cell layouts are used, then standard programming can be performed, but the footprint is too large for small-area applications
Solution Approach 1:
The patent merges the source line function with the bit line structure, allowing bit lines to serve dual purposes as both data access lines and programming lines. This merging eliminates redundant conductors and reduces the space required for memory cell interconnections, achieving a compact footprint suitable for small-area applications while maintaining standard programming capability.
Solution Approach 2:
By making the bit line universal—capable of serving as both a data line during reads and a programming line during writes—the patent eliminates the need for separate dedicated source lines. This multi-functionality approach significantly reduces the memory cell array footprint, enabling deployment in space-constrained applications without sacrificing programming functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in memory cells with a significantly reduced footprint (up to 50% smaller) and improved longevity, enabling low-power operation and increased program/erase cycling, while maintaining compatibility with advanced processing nodes like the 65 nm node or lower.
Implementation Method 1
using the Fowler-Nordheim programming technique, which allows for lower voltage operation
Data Source
AI summary
A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.