Common-Source MOSFET Packaging Structure for Conductive Loss Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MOSFET semiconductor packaging structures face significant conductive loss and limited flexibility due to separate packaging of MOSFET ICs, which restricts the use of smaller packaging substrates and complicates die location modifications.
Innovation Solution
A common-source packaging structure integrates two MOSFET dies into a single packaging body with electrically connected source electrode pads, reducing conductive loss and allowing for more compact substrate size, while enabling flexible gate electrode pad arrangement for improved IC layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two or more MOSFET ICs are separately packaged and connected by conductive wires, then each IC can be independently manufactured, but the conductive path becomes long resulting in greater conductive loss and occupies significant footprint area
Solution Approach 1:
The patent merges multiple MOSFET dies into a single packaging structure where the dies are mounted on a common substrate with their source electrode pads electrically connected to a common-source region. This integration eliminates the need for long external conductive wires between separately packaged ICs, thereby reducing conductive loss while maintaining independent manufacturability of each die.
2Ease of manufacture
If two or more MOSFET ICs are separately packaged and connected by conductive wires, then each IC can be independently manufactured, but the packaging substrate footprint becomes large restricting usage of smaller substrates
Solution Approach 1:
The patent combines multiple MOSFET dies and their connection structures into a single integrated packaging substrate. By mounting multiple dies on one substrate and using a common-source connection architecture, the total packaging area is significantly reduced compared to separate packaging approaches, enabling use of smaller substrates.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional arrangement of MOSFET dies on the substrate, rather than only planar placement. This dimensional approach allows more efficient use of substrate area, reducing the footprint while accommodating multiple independently manufactured dies.
3Adaptability or versatility
If the location of the die in the packaging structure needs to be changed, then circuit layout flexibility is improved, but the electrode pad location makes modification more difficult
Solution Approach 1:
The patent designs the packaging structure with a common-source region that can accommodate multiple MOSFET dies with their source electrode pads connected to this universal connection point. This universal architecture allows flexible placement of dies in different locations on the substrate while maintaining consistent electrical connections, enabling circuit layout modifications without complicating electrode pad connections.
Data Source
AI summary
A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.