3D Memory Common Source Structure Stress Reduction
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Solution Overview
Problem
The existing 3D NAND memory devices face challenges such as wafer warpage, lithography defocusing, and cladding misalignment due to the high stress of metal tungsten in the common source connecting structure, which affects the fabrication process and memory density.
Innovation Solution
A method for forming a 3D memory device involving the formation of an alternating conductive/dielectric stack, plasma treatment, doping, and rapid thermal crystallization processes to create a polysilicon layer with a tungsten layer, reducing wafer stress and improving conductivity and device mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal tungsten is deposited into the common source contact hole to form the CSL connecting structure, then the electrical conductivity is improved, but the wafer stress becomes uneven causing wafer warpage, lithography defocusing, and cladding misalignment
Solution Approach 1:
The patent replaces pure metal tungsten with a composite structure consisting of a polysilicon layer and a tungsten layer. The polysilicon layer serves as the base common source structure, while the tungsten layer is selectively deposited in contact holes to provide enhanced conductivity only where needed. This composite approach maintains electrical performance while reducing overall stress on the wafer.
Solution Approach 2:
Instead of making the entire common source structure highly conductive (which would require tungsten throughout), the patent applies tungsten locally only in the contact holes where electrical connection is required. The polysilicon layer provides the structural framework and baseline conductivity, while localized tungsten deposition provides additional conductivity precisely where electrical connection is needed, minimizing unnecessary stress accumulation.
2Reliability
If metal tungsten is deposited into the common source contact hole, then the electrical conductivity is improved, but wafer warpage occurs affecting fabrication process stability
Solution Approach 1:
The patent uses a composite structure of polysilicon and tungsten layers. The polysilicon layer has lower stress and provides structural stability, while the tungsten layer is confined to contact holes providing localized conductivity enhancement. This composite approach prevents the uniform stress distribution that causes wafer warpage while maintaining necessary electrical conductivity.
Solution Approach 2:
The common source structure is segmented into two functional parts: a polysilicon base layer that provides structural support and distributed conductivity, and discrete tungsten segments deposited only in contact holes for enhanced local conductivity. This segmentation prevents the accumulation of stress across the entire wafer surface, maintaining wafer flatness during fabrication.
3Reliability
If the common source structure is formed with high conductivity material, then the device mobility is improved, but the stress distribution becomes uneven causing process problems
Solution Approach 1:
The patent applies high-conductivity tungsten material locally only where electrical connection is required (in contact holes), rather than throughout the entire common source structure. The polysilicon layer provides sufficient baseline conductivity for device mobility while having lower stress characteristics. This localized application of high-conductivity material improves device mobility without generating widespread stress-induced process problems.
Solution Approach 2:
The composite structure combines polysilicon (lower stress, adequate conductivity) with localized tungsten (high conductivity, high stress) such that the beneficial electrical properties of tungsten are obtained only where needed, while the bulk of the structure maintains the low-stress characteristics of polysilicon, preventing stress-induced process problems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces wafer stress and enhances the conductivity and mobility of the common source structure, addressing the issues of wafer warpage and misalignment, and improving the overall performance of the 3D memory device.
Implementation Method 1
performing a plasma treatment followed by a first doping process to the first conductive layer
Implementation Method 2
performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer
Data Source
AI summary
A method for forming a 3D memory device is disclosed. The method comprises: forming an alternating conductive/dielectric stack on a substrate; forming a slit vertically penetrating the alternating conductive/dielectric stack; forming an isolation layer on a sidewall of the slit; forming a first conductive layer covering the isolation layer; performing a plasma treatment followed by a first doping process to the first conductive layer; forming a second conductive layer covering the first conductive and filling the slit; performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer; removing an upper portion of the first conductive layer and the second conductive layer to form a recess in the slit; and forming a third conductive layer in the recess.