Common TSV for Multi-Die Stack Interconnection
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Solution Overview
Problem
Stacking multiple dies or wafers in a vertical arrangement poses challenges due to the need for precise alignment and flat, smooth bonding surfaces, and the impracticality of using multiple through-silicon vias (TSVs) for electrical connections beyond two or three layers, which can lead to inefficiencies and inaccuracies in forming reliable interlayer connections.
Innovation Solution
The technique involves forming conductive pads with interior areas free of conductive material on each die or wafer, allowing for the creation of a through-silicon via (TSV) that electrically couples all devices in a stack, with the interior area dimensions and shapes varying to accommodate misalignments and overshadowing effects, and optionally using an intentional offset in die placement to ensure complete interlayer connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple through-silicon vias (TSVs) are used for electrical connections in stacked dies beyond two or three layers, then electrical connection reliability improves, but device complexity and manufacturing difficulty increase significantly
Solution Approach 1:
The patent merges multiple separate TSV structures into a single common cavity that extends through all stacked dies. Instead of implementing individual TSVs for each die interface, a unified cavity structure penetrates through the entire stack, reducing the number of discrete interconnection elements and simplifying the overall device architecture while maintaining electrical connection reliability across multiple layers.
Solution Approach 2:
The patent transitions from a two-dimensional planar interconnection approach to a three-dimensional vertical cavity structure. By creating a common cavity that extends through the vertical dimension of the entire die stack, the invention enables electrical connections across multiple layers without requiring multiple separate via structures at different heights, thus reducing complexity.
2Reliability
If precise alignment and flat, smooth bonding surfaces are required for stacking multiple dies, then interlayer connection reliability improves, but manufacturing precision requirements and process complexity increase
Solution Approach 1:
The patent performs preliminary formation of the common cavity structure through all stacked dies before final bonding. By pre-establishing the cavity geometry and positioning features in each die, the invention enables subsequent alignment and bonding processes to proceed with reduced precision requirements, as the cavity structures serve as self-aligning features that accommodate minor misalignments.
3Device complexity
If a common interconnection structure is formed through all stacked dies, then device complexity reduces and manufacturing simplifies, but the ability to accommodate misalignments and ensure complete interlayer connection becomes more challenging
Solution Approach 1:
The patent modifies the geometric parameters of the common cavity structure, including its dimensions, shape, and positioning, to optimize its ability to accommodate misalignments. By adjusting cavity parameters such as lateral offsets, depths, and cross-sectional areas in different stacked dies, the invention ensures complete interlayer connection while maintaining manufacturing simplicity.
Solution Approach 2:
The patent employs asymmetric cavity configurations in different stacked dies rather than uniform symmetric structures. By introducing intentional asymmetries in cavity positioning and dimensions, the invention compensates for expected misalignments during stacking, ensuring that the common interconnection structure successfully connects all layers despite manufacturing tolerances.
Data Source
AI summary
Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.