Common Virtual Address Mapping for Heterogeneous Processor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory management systems in multiprocessor computing devices limit the effectiveness of offloading operations to auxiliary processors, leading to inefficient communication and performance issues due to independent memory management by each processor, which prevents direct communication of pointers and virtual addresses between heterogeneous processors.
Innovation Solution
Configuring multiprocessor systems to assign the same virtual address for shared memory regions across processors, allowing direct communication and reducing the need for extensive system bus usage by enabling processors to map physical pages using common virtual addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each processor independently manages its own memory space, then memory management autonomy is maintained, but communication efficiency between processors deteriorates due to extensive system bus usage
Solution Approach 1:
The patent merges the memory address spaces of multiple heterogeneous processors by establishing a common virtual address that both processors can use to access the same physical memory region. This combining of address spaces eliminates the need for extensive address translation and system bus usage during inter-processor communication, while each processor maintains its own memory management unit and address space management capabilities.
Solution Approach 2:
The patent introduces a memory management intermediary mechanism that coordinates address mapping between heterogeneous processors. This intermediary establishes the common virtual address mapping in a way that allows both processors to access shared memory regions efficiently without requiring each processor to independently manage the entire memory space, thus maintaining autonomy while improving communication.
2Device complexity
If heterogeneous processors use different virtual address mappings, then processor independence is preserved, but performance deteriorates due to increased operations and data communication via system buses
Solution Approach 1:
The patent combines the virtual address mappings for specific memory regions across heterogeneous processors by establishing a common virtual address that maps to the same physical memory location in both processors. This reduces the number of address translation operations and system bus transactions required during inter-processor communication, thereby improving power efficiency while preserving processor independence through separate memory management units.
Solution Approach 2:
The patent changes the address mapping parameters by establishing a common virtual address that both heterogeneous processors can use. This parameter change optimizes the address translation process by reducing the number of translation operations needed, thereby decreasing power consumption associated with memory management operations while maintaining processor independence.
3Ease of operation
If processors communicate through extensive system bus usage, then data exchange between processors is enabled, but performance deteriorates due to increased communication overhead
Solution Approach 1:
The patent merges the address spaces of heterogeneous processors by establishing a common virtual address that both processors can use to access shared memory regions directly. This eliminates the need for extensive system bus usage during data exchange, as processors can access shared memory through their own address spaces without requiring frequent bus transactions, thereby improving processing performance while maintaining data exchange capability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Mobile computing devices may be configured to compile and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system by reading and writing information to a shared memory. A first process (P1) on the applications processor may request address negotiation with a second process (P2) on the auxiliary processor, obtain a first address map from a first operating system, and send the first address map to the auxiliary processor. The second process (P2) may receive the first address map, obtain a second address map from a second operating system, identify matching addresses in the first and second address maps, store the matching addresses as common virtual addresses, and send the common virtual addresses back to the applications processor. The first and second processes (i.e., P1 and P2) may each use the common virtual addresses to map physical pages to the memory.