Communication Circuit Using N-Phase Clocks for Low Latency
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Solution Overview
Problem
Existing communication circuits between function blocks in semiconductor integrated circuits face challenges with high latency, increased hardware requirements, and power consumption due to the need for multiple pipeline stages and buffering, especially when operating at high frequencies.
Innovation Solution
A communication circuit utilizing N number of communication means, each operating at a second clock signal with a frequency of 1/N of the first clock signal and a phase difference of 360/N degrees, allowing for efficient data transfer with reduced hardware and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipeline technique is used to increase operating frequency of communication circuit, then communication speed is improved, but circuit area and power consumption increase due to multiple pipeline stages
Solution Approach 1:
The communication circuit is divided into N pipeline stages, each operating at a reduced clock frequency of 1/N of the function block clock. This segmentation allows the use of lower-speed, simpler circuit elements in each stage while maintaining overall high throughput through parallel processing of multiple data packets.
2Speed
If multiple pipeline stages are inserted to achieve high operating frequency, then communication speed is improved, but power consumption increases
Solution Approach 1:
The communication circuit uses periodic clock signals with frequency 1/N of the function block clock to drive each pipeline stage. This periodic action at lower frequency reduces dynamic power consumption in each stage while the overall system achieves high effective communication speed through the pipeline architecture processing multiple packets sequentially.
3Speed
If pipeline registers are used to divide signals into sub-signals, then operating frequency is improved, but latency increases
Solution Approach 1:
Each pipeline stage performs preliminary processing of data packets before passing them to the next stage. The first pipeline stage receives and processes the entire data packet, then sequentially processes subsequent packets. This preliminary action in each stage reduces the overall latency compared to traditional pipeline registers that simply divide signals without processing.
4Productivity
If N times larger data width is used in communication circuit, then throughput is maintained at low frequency, but hardware requirements increase
Solution Approach 1:
The communication circuit maintains continuous useful action by processing multiple data packets sequentially through the pipeline stages. Each stage continuously processes one packet at a time, and the pipeline architecture ensures that while one packet is being processed in a stage, other packets are being processed in parallel in different stages, maintaining high throughput without requiring expanded data width.
Data Source
AI summary
Provided is a communication circuit (10) connected with a plurality of function blocks (A, B) that perform processing based on a first clock signal, and mediates communication between the function blocks (A, B). The communication circuit (10) includes N number of communication means, where N is a positive integer, having the same data width as communication data output from the function blocks, and each of the N number of communication means performs communication processing based on N number of second clock signals specified by 1/N of a frequency of the first clock signal, respectively corresponding to the N number of communication means and having a phase difference of 360/N degrees from each other. This makes it possible to provide a communication circuit between function blocks in which the amount of necessary hardware and power consumption is small, the timing design is easy, and the communication latency is low.