Communication Device Clock Circuit Power Management

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Solution Overview

Problem

Current wireless communication devices face high power consumption due to the need for continuous clock phase enablement in Hunt Mode, which is not optimized for periods with large gaps in data transmission, leading to inefficiencies in power management.

Innovation Solution

Introducing a new power-saving mode called Hunt-Idle, where phase clocks are disabled between frames and only enabled upon detection of a new frame, allowing correlation over a reduced number of bits and enabling edge detection logic to manage power consumption independently of the Line Driver.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Hunt Mode continuously enables all phase clocks to search for synchronization patterns, then synchronization reliability is improved, but power consumption increases

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically switches between Hunt Mode and Hunt-Idle Mode based on synchronization state. In Hunt Mode, all phase clocks are enabled for comprehensive synchronization search. After synchronization is achieved, the system transitions to Hunt-Idle Mode where only the active phase clock remains enabled, dynamically adapting clock enablement to current operational needs and reducing power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic synchronization checks after initial synchronization. The Line Receiver periodically monitors for synchronization patterns while in Hunt-Idle Mode, maintaining only minimal clock activity. This periodic action ensures synchronization reliability is maintained while avoiding continuous full-power operation of all phase clocks.

Inventive Principle:
Principle #19Periodic action

2Reliability

If all phase clocks are enabled continuously in Hunt Mode, then data reception reliability is improved, but battery life decreases

Engineering Contradiction:
Improvedata reception reliabilityVSAvoidbattery life
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent extracts and disables unused phase clocks after synchronization is achieved. Only the single active phase clock required for current data reception remains enabled, while all other phase clocks are turned off. This extraction of unnecessary clock operations significantly reduces power consumption and extends battery life while maintaining data reception reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system changes the operational parameter of phase clocks from 'enabled' to 'disabled' based on synchronization state. After initial synchronization, the parameter change reduces the number of active phase clocks from multiple to one, optimizing the balance between reception reliability and power consumption for extended battery operation.

Inventive Principle:
Principle #35Parameter changes

3Use of energy by moving object

If Hunt-Idle Mode disables phase clocks between frames, then power consumption is reduced, but synchronization complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidsynchronization complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The Line Receiver autonomously manages phase clock enablement based on frame detection. Upon detecting a new frame's synchronization pattern, the receiver automatically re-enables the appropriate phase clock without external intervention. This self-service approach handles the added synchronization complexity internally while maintaining the power-saving benefits of Hunt-Idle Mode.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements feedback through periodic synchronization pattern monitoring. The Line Receiver continuously checks for synchronization patterns in incoming frames and uses this feedback to determine when to re-enable phase clocks. This feedback mechanism manages synchronization complexity by triggering clock enablement only when actually needed, rather than maintaining continuous complex clock management.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8473000B2Communication device, integrated circuit and method therefor
Publication Date: 2013.06.25 NXP USA INC
  • US8473000B2 patent drawing
  • US8473000B2 patent drawing
  • US8473000B2 patent drawing

AI summary

A communication device is capable of supporting communication compliant with a Dual-Mode 2.5G and 3G interface baseband-radio frequency interface standard and comprises a data interface operably coupled to a number sub-systems and a clock circuit generating a plurality of clock phases for supporting communication there between. At least one of the number of sub-systems comprises a line driver and a line receiver; wherein the communication device is characterized in that the line receiver determines an end of a received data frame sent across the data interface and in response thereto switches itself off.