Communication Interface Architecture for Master-to-Master and Slave-to-Master Synchronization
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Solution Overview
Problem
Communication interfaces in integrated circuits face synchronization issues and increased peak current consumption due to unknown clocking schemes and deepened read FIFO latches when acting as slaves or masters in master-to-slave, master-to-master, or slave-to-master configurations with other integrated circuits.
Innovation Solution
The communication interface includes multiple input/output circuitries with programmable single-ended and differential/single-ended input/output modules, a centralized pointer generation block, and delay-locked loops to support both free-running and strobe-based clock signals, allowing the interface to function as either a slave or master, and reducing read FIFO latch switching by ensuring only two entries are toggled per clock edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the communication interface bonds multiple input/output circuitries to store commands and data spanning a large width, then the storage capacity is improved, but the peak current consumption increases undesirably
Solution Approach 1:
The interface is divided into multiple independent input/output circuitries (e.g., four 36-gigabit circuitries) that can operate independently. Each circuitry has its own storage resources, allowing the system to achieve large total storage capacity (144 bits) without requiring all circuitries to switch simultaneously, thereby reducing peak current consumption compared to a monolithic design.
Solution Approach 2:
The interface dynamically configures the number and width of active input/output circuitries based on communication requirements. The system can bond one, two, three, or four circuitries depending on the data width needed, allowing flexible adaptation between storage capacity and power consumption needs.
2Adaptability or versatility
If the communication interface receives commands from an additional integrated circuit without knowledge of when commands will arrive, then the adaptability to different communication configurations is improved, but synchronization problems occur
Solution Approach 1:
A buffer memory (FIFO) is introduced as an intermediary between the additional integrated circuit and the interface logic. The buffer absorbs timing variations and stores incoming commands temporarily, allowing the interface to handle asynchronous command arrivals from master-to-master or slave-to-master configurations without synchronization issues.
Solution Approach 2:
The buffer memory pre-allocates storage space and is ready to receive commands before they arrive. The interface is pre-configured to handle both free-running and strobe-based clocking schemes, allowing it to immediately process incoming commands regardless of when they arrive or which clocking scheme is used.
Data Source
AI summary
A communication interface includes one or more input/output circuitries, each input/output circuitry including a pointer generation block that controls write pointers of a respective input/output circuitry and read pointers of the respective input/output circuitry. Each input/output circuitry also includes input/output buffers communicatively coupled to the pointer generation block. Each input/output circuitry further includes a receive delay-locked loop that provides a clock signal to the plurality of input/output buffers. Each input/output circuitry also includes one or more transmit delay-locked loops that delay the clock signal.