Communication Testing Circuit Timing Margin Quantification
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Solution Overview
Problem
Existing methods for testing high-speed serial communication in consumer electronics either take too long for 100-percent testing prior to shipment or fail to quantify the timing margin, leading to potential defective products being shipped.
Innovation Solution
A communication testing circuit with a transmitting unit that generates a modulated clock signal and pseudo-random pattern, and a receiving unit with a clock and data recovery circuit that recovers the pattern and compares it to a preset, allowing for quantitative decision of the timing margin, using standard equipment to reduce EMI and eliminate the need for special instruments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If waveform measurements using an oscilloscope are performed to quantitatively evaluate timing margin, then measurement precision is improved, but productivity deteriorates due to time-consuming measurements
Solution Approach 1:
The patent uses a pseudo-random pattern generator to create a test signal that copies the characteristics of actual high-speed serial communication data. This test pattern is processed through the Device Under Test (DUT) and compared with the original pattern to evaluate timing margin, replacing the need for complex oscilloscope waveform measurements while maintaining measurement accuracy and enabling rapid 100-percent testing.
2Productivity
If pseudo-random pattern comparison is used to test serial communication, then productivity is improved for 100-percent testing, but measurement precision deteriorates as timing margin cannot be quantitatively determined
Solution Approach 1:
The patent introduces a delay variable as an intermediary parameter. By systematically varying the delay time in the test circuit and observing at which delay points errors occur in the pseudo-random pattern comparison, the system can quantitatively determine the timing margin. This intermediary approach enables both rapid testing and precise timing margin evaluation.
3Measurement precision
If special measuring instruments are used for timing margin evaluation, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a self-service testing approach where the Device Under Test (DUT) itself generates the test signals and performs the measurements using its own internal resources. The DUT includes a pseudo-random pattern generator, delay variable, and error detector that work together to evaluate timing margin without requiring external specialized measuring instruments, thereby reducing device complexity while maintaining measurement precision.
Data Source
AI summary
Provided is a communication testing circuit that includes a transmitting unit including a spread spectrum clock generator that generates a modulated clock signal by modulating a reference clock signal, a pseudo-random binary sequence generator that generates a pseudo-random pattern, and a signal generator that generates a transmission signal by modulating the pseudo-random pattern based on the modulated clock signal, a receiving unit including a clock and data recovery circuit that receives the transmission signal and recovers the pseudo-random pattern from the transmission signal, and a detector that compares the recovered pseudo-random pattern with a preset pseudo-random pattern and outputs a signal indicating error information, and a control unit that counts a number of errors from the signal indicating error information input from the receiving unit and decides a timing margin based on a counting result.