Compact 3D-IC Package Embedding Die in TSV Interposer
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density input/output (I/O) configurations while maintaining a compact footprint in 3D-IC designs, particularly with the increased complexity and power consumption associated with through-silicon via (TSV) technology and silicon interposers.
Innovation Solution
A compact semiconductor 3D-IC structure is developed, integrating TSVs and interposer substrates to embed additional die between exposed TSV structures, enabling high-density I/O designs through redistribution layers (RDLs) and wire bonding, which also facilitates improved heat dissipation and heterogeneous system integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If TSV technology and silicon interposers are used to increase I/O density, then I/O count and system integration are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent embeds additional die within the substrate between exposed TSV structures, creating a nested configuration where smaller die are placed inside the space occupied by the substrate and TSV array. This nesting approach increases I/O density without proportionally increasing overall device complexity, as the embedded die utilize otherwise wasted space in the TSV interposer structure.
Solution Approach 2:
The patent transitions from a conventional two-dimensional I/O arrangement to a three-dimensional configuration by embedding die within the substrate volume between TSV structures. This dimensional change allows I/O elements to be arranged in multiple layers and depths, significantly increasing I/O count without linearly increasing the device footprint or structural complexity.
2Quantity of substance
If more TSVs and interposer substrates are integrated to achieve high-density I/O, then I/O density increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent forms TSV structures and prepares the substrate with exposed TSV ends before embedding the additional die. This preliminary action of creating the TSV infrastructure first allows for standardized, high-volume manufacturing of the substrate-TSV assembly, which can then be combined with pre-fabricated embedded die in a subsequent bonding step, thereby managing manufacturing complexity through process decomposition.
Solution Approach 2:
The patent divides the final high-density I/O structure into separate manufacturable components: the substrate with TSV array, the embedded die, and the redistribution layers. Each component can be manufactured and tested independently using existing processes, reducing overall manufacturing complexity compared to attempting to fabricate the complete integrated structure in a single complex process.
3Area of stationary object
If the substrate area is reduced to maintain compact footprint, then device size decreases, but available space for TSVs and embedded die is reduced
Solution Approach 1:
The patent compensates for reduced substrate area by utilizing the third dimension - embedding die within the substrate thickness and arranging TSV structures in dense three-dimensional patterns. This vertical and depth-based arrangement of components allows high I/O density to be achieved in a compact footprint by exploiting volumetric space rather than relying solely on planar area expansion.
Solution Approach 2:
The patent nests embedded die within the substrate volume between TSV structures, effectively using the substrate and TSV array as a container framework. This nesting maximizes the utilization of available space within the compact footprint, as the embedded die occupy the internal volume of the substrate-TSV structure rather than requiring additional external space.
4Quantity of substance
If TSV structures are densely packed to increase I/O density, then I/O count increases, but interconnect routing and cell placement complexity increase
Solution Approach 1:
The patent introduces redistribution layers (RDL) as intermediary structures between the densely packed TSVs and the embedded die. These RDLs provide a flexible routing plane that can redistribute signals from the dense TSV array to the appropriate embedded die contact pads, thereby decoupling the TSV density from the routing complexity and allowing dense TSV packing without proportionally increasing interconnect routing difficulty.
Data Source
AI summary
A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.