Compact Arithmetic Elements for Low-Precision High-Range Computing
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Solution Overview
Problem
Conventional computing architectures inefficiently utilize transistors, limiting the ability of software to harness the full computing power of modern silicon chips due to a focus on high precision arithmetic, which is costly and not necessary for many applications.
Innovation Solution
Implementing low precision high dynamic range (LPHDR) processing elements that perform arithmetic operations, using logarithmic or analog representations to maximize the number of operations per unit of silicon area, enabling massively parallel computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional high precision arithmetic elements are used, then computational accuracy is improved, but the number of operations per unit time and unit area deteriorates
Solution Approach 1:
The patent employs low-precision arithmetic elements that are computationally inexpensive and can be densely packed. These elements sacrifice some precision but enable massively parallel operations, allowing the system to perform many more operations per unit time by using numerous less-precise units rather than fewer highly-precise units.
Solution Approach 2:
The patent divides the computational task into many small parallel operations performed by numerous low-precision elements. By segmenting the overall computation across many independent units operating in parallel, the system achieves high throughput despite each individual unit having limited precision.
2Measurement precision
If conventional high precision arithmetic elements are used, then computational accuracy is improved, but the amount of silicon area required deteriorates
Solution Approach 1:
Low-precision arithmetic elements occupy significantly less silicon area than high-precision elements. The patent leverages this by deploying a large array of these compact elements, achieving massive parallelism within a limited area while accepting reduced precision in exchange for area efficiency.
Solution Approach 2:
The patent changes the precision parameter of the arithmetic elements from high to low, which directly reduces the area each element occupies on the silicon chip. This parameter change enables fitting many more elements into the same area, increasing overall computational throughput.
3Productivity
If low precision arithmetic is used, then the number of operations per unit area is improved, but computational accuracy deteriorates
Solution Approach 1:
The patent segments the computational workload across many low-precision elements operating in parallel. By distributing the computation rather than requiring high precision in each individual element, the system achieves high area efficiency while maintaining acceptable overall accuracy through the aggregate result of many parallel operations.
Solution Approach 2:
The patent uses many copies of simple low-precision arithmetic elements rather than fewer complex high-precision elements. These replicated simple units can be densely packed on the chip, achieving high operations-per-area throughput while accepting that each copy has limited precision.
4Productivity
If massively parallel low precision elements are deployed, then computing power per transistor is improved, but the complexity of ensuring adequate precision deteriorates
Solution Approach 1:
The patent applies partial precision where sufficient, and uses redundancy to compensate for individual element imprecision. By performing computations with more elements than strictly necessary and allowing some error accumulation, the system achieves adequate overall precision while maintaining high parallelism and transistor efficiency.
Solution Approach 2:
The patent incorporates precision monitoring and adjustment mechanisms that provide feedback on the accuracy of parallel computations. This feedback allows the system to dynamically adjust the number of parallel elements engaged or the precision level used, managing the complexity of precision assurance while maintaining high computing power per transistor.
Data Source
AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).