Compact Arithmetic Elements for Low-Precision High-Dynamic-Range Computing
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Solution Overview
Problem
Conventional computing systems waste transistors by using high precision arithmetic operations, limiting the ability to harness the full computing power of silicon-based processors, as they are designed to support precise calculations that are not necessary for all applications, leading to inefficiencies in using the available computing resources.
Innovation Solution
Implementing low precision high dynamic range (LPHDR) processing elements that can perform arithmetic operations with a precision of about 0.1% error, allowing for a greater number of operations per unit of time or power, and using logarithmic or analog representations to reduce the area required for arithmetic circuits, enabling massively parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high precision arithmetic operations are used, then calculation accuracy is improved, but transistor utilization efficiency deteriorates
Solution Approach 1:
The patent changes the precision parameter from traditional high precision (32-bit or 64-bit floating point) to low precision (8-bit or 16-bit integers), thereby reducing the complexity of arithmetic operations and increasing transistor utilization efficiency while maintaining sufficient accuracy for many applications
2Productivity
If the number of arithmetic elements is increased, then computing power is improved, but chip area consumption is worsened
Solution Approach 1:
The patent uses simple, replicable low-precision arithmetic element designs that can be copied many times across the chip. Each element uses a standardized simple structure (integer adders, shifters, and multiplexers) that can be densely packed, enabling hundreds or thousands of elements on a single chip without proportionally increasing area
Solution Approach 2:
The computing system is segmented into many independent, simple arithmetic elements that can operate in parallel. Each element is a self-contained unit with minimal internal complexity, allowing efficient tiling and packing to maximize chip area utilization while achieving high aggregate computing power
3Measurement precision
If traditional floating point arithmetic is used, then precision is improved, but operational speed is worsened
Solution Approach 1:
The patent accepts lower precision results (8-bit or 16-bit integers) that are sufficient for many applications, eliminating the need for complex high-precision floating point units. This allows much simpler, faster arithmetic operations that can be executed in fewer clock cycles, thereby increasing operational speed
Data Source
AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).