Compact Arithmetic Elements for Massively Parallel LPHDR Processing
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Solution Overview
Problem
Conventional computing systems inefficiently utilize transistors, performing only a few arithmetic operations per clock cycle due to design priorities on precision and compatibility, limiting the harnessing of inherent computing power despite rapid advancements in silicon technology.
Innovation Solution
Implementing low precision high dynamic range (LPHDR) processing elements that perform arithmetic operations with relatively small resources, allowing for massively parallel computations by representing values with low precision but high dynamic range, such as using logarithmic representations or analog methods, to increase the number of operations per unit time or power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional high precision arithmetic elements are used, then measurement precision is improved, but productivity deteriorates
Solution Approach 1:
The patent changes the precision parameter from conventional high precision (32-bit or 64-bit floating point) to low precision (e.g., 8-bit or 16-bit fixed point or logarithmic representation). This parameter change allows arithmetic elements to perform operations with fewer bits, reducing the complexity and resource requirements of each operation, thereby enabling more operations to be performed per clock cycle while maintaining adequate precision for many applications.
Solution Approach 2:
The patent segments the computational task into multiple lower-precision operations that can be executed in parallel. Instead of using fewer high-precision arithmetic elements, the system uses many more low-precision elements working simultaneously, dividing the overall computational workload across numerous simpler units to achieve higher throughput.
2Measurement precision
If conventional high precision arithmetic elements are used, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent changes the precision parameter to reduce the bit-width required for arithmetic operations. By using low precision representations (such as 8-bit fixed point, 16-bit floating point, or logarithmic formats with limited mantissa bits), each arithmetic element requires significantly fewer transistors to implement the same functional capabilities, thereby reducing device complexity while maintaining sufficient precision for the target applications.
Solution Approach 2:
The patent employs numerous inexpensive, simple arithmetic elements rather than a few complex, high-precision ones. Each low-precision arithmetic element is much simpler and requires fewer transistors, making them computationally 'cheap' in terms of hardware resources. The system compensates for the lower individual precision by using many more such elements in parallel.
3Measurement precision
If conventional high precision arithmetic elements are used, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent changes the precision parameter to low precision, which directly reduces the energy required per arithmetic operation. Low-precision arithmetic elements with fewer bits require less switching activity, smaller signal voltages, and fewer transistors, all of which contribute to lower dynamic power consumption. This enables the system to perform more operations overall while consuming comparable or less total power.
4Measurement precision
If conventional high precision arithmetic elements are used, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent segments the computational workload into many parallel low-precision operations. By dividing the overall computation into numerous independent or loosely coupled tasks that can be executed simultaneously across multiple arithmetic elements, the system reduces the total computation time despite each individual operation having lower precision. The parallel execution compensates for the reduced per-operation precision.
Solution Approach 2:
The patent changes the precision parameter to enable faster operation speeds. Low-precision arithmetic elements can operate at higher clock frequencies due to their simpler internal logic and shorter critical paths. This speed increase, combined with the ability to perform more operations in parallel, reduces the overall computation time for many applications.
Data Source
AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).