Compact Arithmetic Elements for Low-Precision Parallel Processing
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Solution Overview
Problem
Conventional computing systems inefficiently utilize transistors, performing only a few arithmetic operations per clock cycle due to design priorities on precision over power, limiting the ability to harness the full computing potential of modern silicon chips.
Innovation Solution
Implementing low precision high dynamic range (LPHDR) processing elements that perform arithmetic operations with a focus on massively parallel processing, allowing for a significant increase in the number of operations per unit time or power, using logarithmic or analog representations to reduce circuit size and enhance computing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional high precision arithmetic elements are used, then measurement precision is improved, but productivity deteriorates
Solution Approach 1:
The patent segments the arithmetic processing into two distinct types: high precision arithmetic elements for tasks requiring accuracy, and low precision high dynamic range (LPHDR) arithmetic elements for tasks where approximate results suffice. This segmentation allows the system to optimize for either precision or productivity depending on the computational task, resolving the contradiction by enabling parallel processing with different precision levels.
Solution Approach 2:
The patent changes the precision parameter of arithmetic elements dynamically based on application requirements. LPHDR arithmetic elements use reduced precision (e.g., 5-10 bit mantissa instead of 23 bit in IEEE 754) while maintaining high dynamic range through extended exponent ranges. This parameter change enables significantly higher operational throughput while providing adequate precision for many scientific and engineering applications.
2Measurement precision
If conventional high precision arithmetic elements are used, then measurement precision is improved, but use of energy deteriorates
Solution Approach 1:
The patent reduces power consumption by changing the precision parameters of arithmetic elements. LPHDR arithmetic elements use fewer bits for mantissa representation (5-10 bits versus 23 bits in single precision IEEE 754), directly reducing the computational complexity and energy required for arithmetic operations. The extended exponent range compensates for reduced mantissa precision, maintaining adequate accuracy while significantly lowering power consumption.
Solution Approach 2:
The patent segments energy consumption by creating separate high precision and LPHDR arithmetic element pathways. Energy-intensive high precision operations are reserved only for tasks that truly require them, while the majority of computations utilize the lower-power LPHDR elements. This segmentation enables the system to minimize overall power consumption while maintaining capability for high precision when necessary.
3Productivity
If more arithmetic elements are added to increase operations per cycle, then productivity is improved, but device complexity deteriorates
Solution Approach 1:
The patent simplifies the arithmetic element design by changing precision parameters downward. LPHDR arithmetic elements require fewer transistors and simpler circuitry compared to full IEEE 754 compliant elements, because they use reduced mantissa width and simplified normalization logic. This parameter change enables packing many more arithmetic elements into a single chip, increasing parallel operational capacity while actually reducing individual element complexity.
Solution Approach 2:
Instead of increasing precision to improve operational capability, the patent inverts the approach by reducing precision to enable higher operational throughput. By accepting lower precision in exchange for dramatically increased parallelism and reduced circuit complexity per element, the system achieves higher overall productivity with simpler, more scalable architecture.
Data Source
AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).