Compact Bit Line Switch Circuit for 3D NAND Memory
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Solution Overview
Problem
Three-dimensional memory devices face challenges in minimizing the area occupied by bit line switches, which are crucial for efficient memory operations, as existing designs often result in significant space usage due to the large size of switching transistors.
Innovation Solution
A compact bit line switch circuit is designed, where the sense amplifier switch transistor has one active region offset from the gate electrode, and the erase voltage supply transistor has both active regions aligned with the gate electrode, reducing the overall area of the switching transistors by up to 30%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional bit line switch circuit designs are used, then switching functionality is achieved, but the area occupied by switching transistors is large
Solution Approach 1:
The patent applies asymmetry by configuring the sense amplifier switch transistor with one active region offset from the gate electrode while the erase voltage supply transistor has both active regions aligned with the gate electrode. This asymmetric configuration reduces the area occupied by switching transistors by up to 30% while maintaining proper switching functionality through differentiated transistor geometries optimized for their specific operational requirements.
2Productivity
If switching transistor area is reduced, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The patent implements local quality by applying different geometric configurations to different transistors within the switch circuit. The sense amplifier switch transistor uses an offset active region configuration while the erase voltage supply transistor uses an aligned configuration. This localized differentiation allows area reduction and improved device density without requiring complete redesign of the entire switch circuit, thereby managing manufacturing complexity through targeted local optimizations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases the area occupied by the switching transistors, allowing for a higher device density and more compact memory arrays while maintaining efficient switching functionality.
Implementation Method 1
performing a first ion implantation process that implants dopants of a second conductivity type... performing a second ion implantation process that implants additional dopants of the second conductivity type
Data Source
AI summary
A semiconductor structure includes a three-dimensional NAND memory array including bit lines and an array of bit line connection switches. Each of the bit line connection switches includes a series connection of a first field effect transistor and a second field effect transistor that include a common active region. A deep active portion of a first active region of the first field effect transistor is vertically coincident with a first outer sidewall of a first dielectric spacer, and a deep active portion of the common active region is laterally spaced from the first dielectric spacer to provide a compact design the each bit line connection switch.