Compact CAM Cell Using RRAM and FETs for Low Power Lookup
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Solution Overview
Problem
Conventional Content Addressable Memory (CAM) and Ternary CAM (TCAM) devices are limited by large cell size and high power consumption, making them expensive and restricted in capacity and application, despite their fast lookup capabilities.
Innovation Solution
A compact CAM cell design based on bistable elements and FETs, using two RRAM elements and a single matchline per row, with optional techniques such as regulated wordline voltage to inhibit recharge paths, reducing cell size and power consumption while maintaining fast lookup functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional CAM/TCAM cell designs are used, then fast lookup capability is achieved, but cell size becomes large and power consumption becomes high
Solution Approach 1:
The patent segments the memory cell into two separate bistable elements (first and second bistable elements) that store opposite logic values. This segmentation allows the cell to maintain fast lookup capability through differential comparison while reducing the area of individual components. The segmented architecture enables parallel comparison operations with smaller transistor sizes.
Solution Approach 2:
The patent replaces conventional SRAM-based mechanical/electrical switching structures with bistable elements based on resistance switching (RRAM) or other non-volatile memory mechanisms. This substitution reduces the number of transistors required per cell and decreases power consumption while maintaining the fast lookup function through resistive state comparison.
2Speed
If conventional CAM/TCAM cell designs are used, then fast lookup capability is achieved, but power consumption becomes high
Solution Approach 1:
The patent employs periodic precharging of bitlines and matchlines followed by selective discharging during comparison operations. This periodic action allows the cell to consume power only during active lookup operations rather than continuously, significantly reducing overall power consumption while maintaining fast lookup capability when needed.
Solution Approach 2:
The replacement of SRAM with bistable resistance-switching elements reduces static power consumption by eliminating the need for continuous refresh operations. The resistive states are non-volatile, allowing the cell to maintain data without power, and enables lookup operations with lower energy transitions.
3Adaptability or versatility
If TCAM masking capability is implemented, then sub-word masking functionality is achieved, but cell complexity increases
Solution Approach 1:
The patent implements universality by designing the bistable element structure to serve multiple functions: data storage, mask indication, and comparison logic. The same first and second bistable elements that store data bits also provide mask functionality through their resistance states, eliminating the need for separate mask storage structures and reducing overall cell complexity.
Solution Approach 2:
The patent merges the data storage function and mask indication function into a single bistable element structure. The resistive states of the bistable elements simultaneously represent both data values and mask states, combining what would traditionally require separate circuitry into one integrated component, thereby reducing cell complexity while maintaining versatility.
Data Source
AI summary
A content addressable memory device based on an extremely compact design, potentially as small as 16F2 per memory cell. One embodiment is based on cells having two memory storage elements, such as RRAM elements. Each RRAM element and a respective FET are connected in series between a common matchline and a respective bitline. Cell content for each cell is matched against a bit of a search word by applying voltages to the respective bitlines dependent upon bit value and causing one of the two RRAM elements for each cell to discharge the matchline over a low resistance path in event of mismatch between the cell content and the bit. If no “quick” discharge occurs for multiple cells of a row, then a match is detected. In addition, a matchline recharge path to a high voltage bitline is substantially eliminated by controlling the FETs with specific wordline voltages.