Compact Commutation Cell Layout for Low-Inductance Power Converters
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Solution Overview
Problem
Aerospace power electronics converters face limitations in efficiency and power-to-weight ratio due to high parasitic inductance in existing power module topologies, which restricts the potential for improved performance and increased mission range in electric aircraft applications.
Innovation Solution
A power electronics converter design featuring a commutation cell with reduced parasitic inductance, utilizing a multi-layer planar carrier substrate and power semiconductor prepackages with embedded MOSFETs, and a gate driver circuit to enhance efficiency and power density, allowing for higher switching frequencies and voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power module topology is used with conventional electrical connections, then device complexity is reduced and ease of manufacture is improved, but parasitic inductance increases which limits efficiency and switching frequency
Solution Approach 1:
The patent transitions from conventional three-dimensional wire bonding to a two-dimensional planar configuration on a ceramic substrate. Power semiconductor devices, capacitors, and interconnections are arranged in a planar commutation cell, reducing current loop areas and parasitic inductance while maintaining manufacturing feasibility through standardized PCB-like fabrication processes
Solution Approach 2:
The patent integrates multiple commutation cells for different phases directly onto a single ceramic substrate, sharing common DC link connections and ground planes. This merging approach reduces overall parasitic inductance by eliminating external connection paths while consolidating multiple functions into one integrated structure
2Productivity
If parasitic inductance is reduced through design optimizations, then converter efficiency and switching frequency are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent changes the fundamental geometric parameters of the commutation cell by adopting a planar layout with minimized current loop areas. Trace widths, trace spacing, and component placement are optimized to reduce parasitic inductance to below 5 nH, enabling switching frequencies above 50 kHz while using standard ceramic substrate fabrication techniques
Solution Approach 2:
The patent divides the power circuit into modular commutation cells, each handling a specific phase or function. This segmentation allows independent optimization of each cell's parasitic inductance while maintaining overall system functionality and simplifying the manufacturing process through repetitive modular units
3Loss of energy
If converter efficiency is increased to improve aircraft performance, then energy loss is reduced, but weight sensitivity in aerospace applications requires compact design that conflicts with traditional power module layouts
Solution Approach 1:
The patent uses planar integration to reduce the vertical height of the converter by eliminating multi-layer wire bonding structures. All components are mounted on the same plane of the ceramic substrate, reducing overall converter volume while achieving below 5 nH parasitic inductance and above 95% efficiency
Solution Approach 2:
The patent nests multiple functional elements within a compact planar footprint by arranging power devices, capacitors, and interconnections in a space-efficient configuration on the ceramic substrate, maximizing power density while maintaining low parasitic inductance
Data Source
AI summary
A power electronics converter may include a converter commutation cell having a power circuit and a gate driver circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is included in a power semiconductor prepackage, each prepackage including one or more power semiconductor switching elements embedded in a solid insulating material, each power semiconductor switching element having at least three terminals including a gate terminal. The gate driver circuit is electrically connected to and configured to provide switching signals to the gate terminal of each of the at least one power semiconductor switching element. A peak rated power output of the power electronics converter is greater than 25 kW and a value of a converter parameter α is less than or equal to 5 pHm3.