Compact Charge Trap Memory via Tunnel Oxide Liner and Spacer
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Solution Overview
Problem
Traditional semiconductor memory devices face challenges with high cost, large footprint, and limited programmability due to the need for additional masks and single-time programming capabilities, which hinder their use in low-cost, small-size products like portable electronics.
Innovation Solution
A method involving the formation of a tunnel oxide liner and charge-trapping spacers on both sides of the gate stack, allowing for multiple-time programming without additional masks, achieved by configuring the spacers to store, remove, and determine charges using specific voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional memory structures (floating gate, merged nitride spacers, split-gate) are used, then programming capability and storage function are achieved, but footprint area increases due to gate-to-gate limitations, overlay tolerance requirements, or addition of select transistors and control gates
Solution Approach 1:
The patent transitions from planar 2D memory structures to a 3D vertical structure by forming tunnel oxide liners and CT spacers on the side surfaces of the gate stack. This vertical utilization of space allows charge trapping to occur in the third dimension, reducing the footprint area while maintaining programming capability through multiple charge trap locations at different heights along the gate stack sidewalls.
Solution Approach 2:
The patent embeds the charge trapping functionality within the existing gate stack structure by forming tunnel oxide liners and CT spacers on the side surfaces of the gate stack. The CT spacers are nested between the gate stack and the source/drain regions, utilizing the vertical space that would otherwise be empty, thereby achieving multiple-time programming without increasing the lateral footprint.
2Ease of manufacture
If additional masks are used for fabrication (as in split-gate memory), then multiple-time programming and compact structure are achieved, but manufacturing complexity and production cost increase
Solution Approach 1:
The patent combines the charge trapping structure formation with the existing gate stack fabrication process. The tunnel oxide liners and CT spacers are formed on the side surfaces of the gate stack using the same deposition and etching steps already required for the gate stack, eliminating the need for additional masks while enabling multiple-time programming capability.
Solution Approach 2:
The gate stack structure serves multiple functions: it acts as both the control electrode for the memory cell and as a template for forming the charge trapping structures. The side surfaces of the gate stack are utilized to form tunnel oxide liners and CT spacers, allowing the same structural element to provide both control and charge trapping functionality without requiring separate dedicated structures.
3Adaptability or versatility
If traditional charge storage mechanisms are used, then single-time programming is achieved with simple structure, but device updates become impossible and functionality is limited
Solution Approach 1:
The patent divides the charge trapping functionality into multiple discrete CT spacers located at different positions along the gate stack sidewalls. Each CT spacer can independently store charges, enabling multiple programming events. This segmentation of the charge storage function into multiple spatially separated traps allows for multiple-time programming while maintaining a relatively simple overall structure that builds upon the conventional gate stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of low-cost, compact, multiple-time programmable memory devices that do not require additional masks, addressing the limitations of traditional memory devices by enabling efficient charge management and reducing production costs.
Implementation Method 1
forming a tunnel oxide liner on side surfaces of gate stack and on the substrate on each side of the gate stack
Implementation Method 2
forming a charge-trapping (CT) spacer on each tunnel oxide liner... store charges when a low voltage is applied to the second contact and a program voltage is applied to the first contact
Data Source
AI summary
A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.