Compact CMOS Guard Ring Structure for Latch-Up Prevention
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Solution Overview
Problem
Conventional guard ring structures in CMOS integrated circuits are space-consuming, increasing die size and cost due to the large silicon area required, particularly because of the minimum spacing needed between P-type and N-type buried layers.
Innovation Solution
A compact guard ring structure is implemented with an N-type guard ring surrounded by inner and outer P-type guard rings, where the N-type guard ring is formed with interleaving deep N-wells and P-wells that are electrically shorted, and P-well contacts are integrated into the N-type guard ring to eliminate the need for separate P-taps in the P-type guard rings, reducing the silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional double guard ring structure is used, then latch-up prevention is achieved, but silicon area increases
Solution Approach 1:
The patent combines the P-type guard ring and N-type guard ring into a single integrated structure where P-well regions and N-well regions are formed in an interleaved pattern within the same epitaxial layer, eliminating the need for separate guard ring structures and reducing silicon area
Solution Approach 2:
The patent embeds the P-type guard ring regions within the N-type guard ring structure by forming P-wells inside the N-well epitaxial layer, creating a nested configuration that reduces the overall area required for latch-up prevention
2Reliability
If minimum spacing between P-type and N-type buried layers is maintained, then device reliability is ensured, but die size increases
Solution Approach 1:
The patent transitions from a planar spacing approach to a vertical stacking approach by forming P-wells and N-wells in different layers of the epitaxial structure, allowing electrical isolation without requiring lateral spacing, thus reducing die size while maintaining reliability
3Reliability
If separate P-taps are used for P-type guard ring, then electrical connectivity is achieved, but device complexity increases
Solution Approach 1:
The patent merges the P-tap contact function into the existing N-type guard ring contact structure by forming the P-well regions adjacent to the N-well contact regions, allowing both P-type and N-type guard rings to share common contact points and reducing the number of separate electrical connections required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compact guard ring structure reduces the silicon area needed for implementation, minimizing die size and preventing latch-up by effectively collecting minority carriers, while maintaining electrical connectivity and reducing surface leakages.
Implementation Method 1
The N-type guard ring of the guard ring structure 16 collects minority carriers (electrons) that may be injected into the substrate 12 by the LDMOS transistor device 22
Implementation Method 2
The P-type guard ring of the guard ring structure 16 further collects majority carriers (holes) that may be generated when electrons injected recombine before they get collected by the N-well 20
Implementation Method 3
N+ diffusion regions 30 are formed in the N-well/deep N-well to form ohmic contact with overlying contacts (not shown) and to reduce the well resistance
Implementation Method 4
The P-type guard ring (P-well 24) is typically connected to ground using P+ diffusion regions to form ohmic contact with overlying contacts (not shown), also referred to as P-taps
Data Source
AI summary
An integrated circuit includes an active device formed in a semiconductor layer of a first conductivity type, a first guard ring of the first conductivity type formed in the semiconductor layer surrounding at least part of the active device; a second guard ring of the second conductivity type formed in the semiconductor layer surrounding the first guard ring and the active device and including comprising alternating first well regions of the first conductivity type and the second well regions of the second conductivity type, the first and second well regions being electrically shorted together and electrically coupled to a ground potential or floating; and a third guard ring of the first conductivity type formed in the semiconductor layer surrounding the second guard ring. The first and third guard rings do not receive direct electrical connection.