Compact CMOS Isolation Using N-Well and Buried Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional CMOS integrated circuits require large silicon area for device isolation due to the use of deep N-well rings, leading to increased die size and cost, while also failing to effectively isolate sensitive analog circuits from noisy digital substrates.
Innovation Solution
A compact CMOS device isolation scheme where an N-well encircles a P-well, with an N-type buried layer formed under the P-well, eliminating the need for a deep N-well ring and reducing silicon area usage, thereby isolating NMOS devices from the substrate without increasing noise coupling to analog circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a deep N-well ring is used for CMOS device isolation, then effective isolation from substrate noise is achieved, but the silicon area occupied by the isolation structure increases
Solution Approach 1:
The patent transitions from a two-dimensional deep N-well ring structure to a three-dimensional structure by forming an N-type buried layer beneath the P-type substrate. This vertical extension into the third dimension (depth) provides the isolation function without requiring additional lateral silicon area, thus resolving the contradiction between isolation effectiveness and area occupation.
Solution Approach 2:
The patent introduces an N-type buried layer as an intermediary structure between the P-type substrate and the circuit blocks. This buried layer acts as a mediator that provides noise isolation to the sensitive analog circuits without requiring the extensive deep N-well ring structure, thereby reducing the silicon area while maintaining isolation effectiveness.
2Object-affected harmful factors
If a deep N-well ring is used for device isolation, then noise isolation is improved, but the die size increases
Solution Approach 1:
The patent extends the isolation mechanism vertically by forming an N-type buried layer beneath the substrate, moving the isolation function from a lateral (2D) deep N-well ring to a vertical (3D) structure. This dimensional change reduces the lateral footprint and die size while maintaining noise isolation performance.
3Reliability
If a deep N-well ring is used for isolation, then substrate noise isolation is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the isolation function into two distinct components: an N-type buried layer formed beneath the substrate and shallow N-wells formed within the circuit blocks. This segmentation allows each component to be optimized independently and simplifies the overall structure compared to a single deep N-well ring, reducing manufacturing complexity while maintaining isolation effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the silicon area required for device isolation, decreases die size, and lowers the cost of integrated circuits while effectively isolating sensitive analog circuits from noisy digital substrates, minimizing noise coupling.
Implementation Method 1
an N-type buried layer is formed under the P-well... isolating NMOS devices from the substrate without increasing noise coupling to analog circuits
Data Source
AI summary
An integrated circuit uses a compact CMOS device isolation scheme which forms a ring of N-well housing PMOS devices to encircle the P-well housing NMOS devices in a circuit block. An N-type buried layer is formed under the P-well and extends partially under the surrounding N-well. The compact CMOS device isolation scheme eliminates the use of a deep N-well ring around the circuit block. Therefore, the circuit blocks of the integrated circuit can be formed with reduced silicon area and the die size for implementing the integrated circuit is reduced.