Compact CMOS Layout Using a Shared Well and Single Gate
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Solution Overview
Problem
Current CMOS systems face challenges in achieving higher packing density and prolonging the validity of Moore's Law, necessitating new approaches for producing semiconductor devices.
Innovation Solution
A compact CMOS structure is fabricated using a semiconductor substrate with material forming rectifying junctions with both field-induced N and P-type semiconductor regions, featuring parallel and adjacent channels with a gate structure offset by insulating material, allowing for voltage inversion between non-rectifying junctions and the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional CMOS structures with separate N and P-type wells are used, then device functionality is achieved, but packing density is limited due to space requirements
Solution Approach 1:
The patent merges the N-type and P-type wells into a single shared well structure. The common well region serves as the substrate for both N-channel and P-channel MOSFETs, eliminating the need for separate wells and thereby increasing packing density while reducing structural complexity
Solution Approach 2:
The common well structure performs multiple functions simultaneously: it serves as the substrate for both N-channel and P-channel devices, provides electrical isolation through the insulating layer, and enables voltage inversion operation. This multi-functionality reduces the overall device footprint
2Area of stationary object
If traditional separate gate structures for N and P channels are used, then independent control is achieved, but area consumption increases
Solution Approach 1:
The patent combines two gate structures into a single integrated gate that controls both N-channel and P-channel MOSFETs. The gate is positioned over the common well and extends to control both channel regions, reducing the total area required while maintaining independent voltage control through separate electrical connections
3Productivity
If conventional CMOS fabrication is used, then standard device performance is achieved, but further scaling to maintain Moore's Law is challenging
Solution Approach 1:
The patent transitions from planar device architecture to a three-dimensional structure with the gate extending over the common well and controlling channels from multiple directions. This dimensional change enables further scaling by utilizing vertical space and improving gate control efficiency, thereby supporting continued adherence to Moore's Law
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a compact CMOS system with improved packing density and energy efficiency, overcoming limitations of conventional CMOS structures by eliminating the need for space-consuming N and P-type wells and allowing for a single gate to control adjacent channels.
Implementation Method 1
material which forms rectifying junctions both N and P-type Field Induced Semiconductor
Data Source
AI summary
CMOS Systems formed in a Semiconductor Substrate and involving use of material that forms a rectifying junction with both N and P-type Field Induced Semiconductor, in combination with, preferably, Parallel and Adjacent Channels subject to control by a Gate removed from said Channels by insulator.