Compact Cu Conductive Features for Stress-Resistant IVR Interconnects
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Solution Overview
Problem
Existing semiconductor devices, particularly integrated voltage regulators (IVR), face reliability issues due to stress-induced delamination and energy wastage, as magnetic films and conductive features experience stress during fabrication and operation, leading to defects and reduced performance.
Innovation Solution
The semiconductor device incorporates compact copper (Cu) material with greater than 97% Cu (111) for conductive features and magnetic layers, featuring reduced height and textured surfaces to mitigate stress and delamination, thereby enhancing conductance and sustaining chip package interaction stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive features and magnetic films are used in IVR devices, then device functionality is achieved, but stress-induced delamination occurs reducing reliability
Solution Approach 1:
The patent changes the crystallographic orientation parameter of copper from conventional orientations to Cu(111) orientation, which fundamentally alters the material's mechanical properties including stress resistance and delamination behavior, thereby improving reliability without sacrificing functionality
Solution Approach 2:
The patent employs composite material structures including copper-magnetite composites and multi-layered interconnect structures with specific material combinations that provide both electrical conductivity and enhanced mechanical strength to resist stress-induced delamination
2Use of energy by moving object
If copper conductive features are used to enhance conductance, then electrical performance improves, but stress and energy wastage increase
Solution Approach 1:
The patent optimizes the crystallographic orientation parameter of copper to Cu(111), which provides superior electrical conductance while simultaneously reducing mechanical stress and energy losses through the unique atomic packing and electron scattering characteristics of this orientation
3Productivity
If conductive features are made smaller to support scaling, then device density increases, but stress concentration and delamination risk increase
Solution Approach 1:
The patent changes the material parameter of copper crystalline orientation to Cu(111), which maintains exceptional electrical conductivity in scaled-down dimensions while providing enhanced mechanical strength and stress distribution that prevents delamination even at reduced feature sizes
Solution Approach 2:
The patent applies local quality enhancement by specifically orienting copper crystals in the (111) direction at critical stress points and interfaces, providing localized stress resistance where needed most while maintaining overall device scaling and density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of compact Cu material reduces stress, delamination defects, and energy wastage, improving the reliability and performance of semiconductor devices by increasing conductance and sustaining chip package interaction stress effectively.
Implementation Method 1
The one or more conductive features include a compact copper (Cu) material including greater than 97% Cu (111)
Data Source
AI summary
A semiconductor device disclosed herein includes an interconnection structure over a substrate, a first magnetic layer over the interconnection structure, one or more conductive features over the first magnetic layer, a dielectric layer over the first magnetic layer and the one or more conductive features, and a second magnetic layer over the dielectric layer. In some embodiments, the one or more conductive features include a textured top surface.