Compact Decoupling Structure Using Stack-Type Capacitors
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Solution Overview
Problem
Conventional AC signals decoupling structures in circuit systems face challenges in minimizing form factor, parasite resistance, and parasite inductance, leading to compromised AC signals decoupling effectiveness due to large decoupling capacitors and conductive traces.
Innovation Solution
A compact decoupling structure is implemented using a stack-type integrated-passive-device die with a stack-type capacitor, where the decoupling unit is placed in a gap between the logic-circuit die and the substrate, utilizing flip-chip pillars and controlled-collapse-chip-connection bumps to reduce height and parasite effects, and employing metal-insulator-metal sandwich layers for high capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large decoupling capacitor is used to provide sufficient capacitance for AC signals decoupling, then the decoupling function is improved, but the form factor of the circuit system increases
Solution Approach 1:
The patent transitions from planar placement of decoupling capacitors on the motherboard surface to three-dimensional stacking within the gap between the circuit unit and substrate. By utilizing the vertical dimension (gap space) rather than only horizontal placement, the design achieves sufficient capacitance without increasing the footprint area, thus resolving the contradiction between decoupling function and form factor.
Solution Approach 2:
The patent embeds multiple decoupling capacitor layers within the gap space, nesting them vertically between the circuit unit and substrate. This nesting approach allows multiple capacitance values to be stacked in the same footprint area, providing sufficient total capacitance while maintaining a compact form factor.
2Reliability
If a long conductive trace is used to connect the decoupling capacitor and the die, then the connectivity is ensured, but the parasite resistance and parasite inductance increase
Solution Approach 1:
The patent extracts the decoupling capacitor from its conventional location on the motherboard and places it directly in the gap adjacent to the die. This extraction eliminates the need for long conductive traces by positioning the capacitor immediately next to the die, thereby removing the source of high parasite resistance and inductance while maintaining electrical connectivity.
Solution Approach 2:
The patent creates a localized decoupling structure by placing the capacitor in immediate proximity to the die within the gap. This local placement ensures that the decoupling function is applied exactly where needed (at the die location) with minimal trace length, reducing parasite effects while maintaining effective connectivity.
3Ease of manufacture
If conventional decoupling structures are used, then the implementation is simple, but the AC signals decoupling effect is compromised due to LC resonant frequency introduction
Solution Approach 1:
By moving the decoupling capacitor into the vertical gap dimension rather than placing it on the motherboard surface, the patent changes the electrical characteristics of the connection path. This dimensional change reduces the loop area and inductance, preventing LC resonant frequency issues while maintaining manufacturing simplicity through standard stacking processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compact decoupling structure achieves a low profile form factor, low parasite resistance, and low parasite inductance, optimizing AC signals decoupling by providing sufficient capacitance while minimizing physical size and interference.
Implementation Method 1
at least one stack-type integrated-passive-device die, and a plurality of third metal contacts, the third metal contacts being formed on the mother die and soldered onto the logic-circuit die, and the at least one stack-type integrated-passive-device die each having a plurality of fourth metal contacts formed thereon and soldered onto the mother die
Data Source
AI summary
A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.