Compact Continuous-Time Delta-Sigma ADC for Lower Loop Delay

Solution Overview

Problem

The conventional continuous-time delta-sigma Analog to Digital Converter (ADC) has a complex structure that wastes layout area and increases loop delay, leading to higher costs and worse system stability.

Innovation Solution

A compact continuous-time delta-sigma ADC design is implemented, featuring a loop filter, a summing circuit with positive and negative summing resistors, a quantizer, and a current Digital to Analog Converter (DAC), where the summing circuit is optimized to reduce layout area consumption and integrate summing functions into the quantizer, reducing current sources and switches, thereby improving stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional continuous-time delta-sigma ADC structure is used, then the ADC can achieve noise shaping and filtering capabilities, but the layout area is wasted and loop delay is increased

Engineering Contradiction:

Improvesystem stabilityVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the summing circuit and quantizer into a single integrated module. The summing voltages are directly compared with reference voltages in the quantizer without separate summing operations, reducing the number of components and interconnections while maintaining the noise shaping and filtering functionality of the delta-sigma ADC

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If a conventional continuous-time delta-sigma ADC structure is used, then the ADC can achieve noise shaping and filtering capabilities, but the layout area is wasted

Engineering Contradiction:

Improvesystem stabilityVSAvoidlayout area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the summing circuit and quantizer into a single integrated module. The summing voltages are directly compared with reference voltages in the quantizer without separate summing operations, reducing the number of components and interconnections while maintaining the noise shaping and filtering functionality of the delta-sigma ADC

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The quantizer is designed to perform multiple functions: it directly compares the summing voltages with reference voltages to generate digital output, and simultaneously provides feedback currents through the merged summing circuit. This multi-functionality eliminates the need for separate dedicated summing circuitry, reducing overall layout area

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If a conventional continuous-time delta-sigma ADC structure is used, then the ADC can achieve noise shaping and filtering capabilities, but loop delay is increased

Engineering Contradiction:

Improvesystem stabilityVSAvoidloop delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the summing circuit and quantizer into a single integrated module. The summing voltages are directly compared with reference voltages in the quantizer without separate summing operations, reducing the number of components and interconnections while maintaining the noise shaping and filtering functionality of the delta-sigma ADC

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The compact structure saves layout area and current consumption while enhancing system stability by maintaining the same difference between summing voltages, allowing the ADC to operate efficiently with reduced complexity.

Implementation Method 1

The loop filter noise-shapes an analog input signal, and then accordingly outputs a positive loop voltage VL+ and a negative loop voltage VL−

Methodology Applied

Scientific EffectNoise shaping:

Implementation Method 2

The positive summing resistor is utilized for transforming a positive feedback current to be a positive feedback voltage, and summing the positive loop voltage and the positive feedback voltage

Methodology Applied

Scientific EffectOhm's law: Ohm's Law

Implementation Method 3

The current DAC is utilized for generating the positive and the negative feedback currents according to the digital output signal

Methodology Applied

Scientific EffectDigital to Analog conversion:

Data Source

PatentUS20110221618A1Continuous-time delta-sigma ADC with compact structure

Publication Date: 2011.09.15 MEDIATEK INC

AI summary

A continuous-time delta-sigma Analog to Digital Converter (ADC) with a compact structure comprises a loop filter, a summing circuit, a quantizer, and a current Digital to Analog Converter (DAC). The loop filter is utilized for receiving and noise-shaping an analog input signal, and accordingly outputting a positive and a negative loop voltages. The summing circuit comprises a positive and a negative summing resistors. The summing resistors are utilized for transforming a positive and negative feedback currents to be a positive and a negative feedback voltages, and summing the loop voltages and the feedback voltages so as to generate a positive and a negative summing voltages, respectively. The quantizer is utilized for outputting a digital output signal according to a difference between the positive and the negative summing voltages. The current DAC is utilized for generating the positive and the negative feedback currents according to the digital output signal.